Display panel
    3.
    发明授权
    Display panel 失效
    显示面板

    公开(公告)号:US08759834B2

    公开(公告)日:2014-06-24

    申请号:US13947459

    申请日:2013-07-22

    CPC classification number: H01L33/0041 H01L27/124 H01L29/458

    Abstract: A display panel includes; a lower gate line, a lower data line disposed substantially perpendicular to the lower gate line, a thin film transistor (“TFT”) connected to the lower gate line and the lower data line, an insulating layer disposed on the lower gate line, the lower data line, and the TFT and having a plurality of trenches exposing the lower gate line and the lower data line, an upper gate line disposed in the trench on the lower gate line, an upper data line disposed in the trench on the lower data line, and a pixel electrode connected to the TFT.

    Abstract translation: 显示面板包括: 下栅极线,基本上垂直于下栅极线设置的下数据线,连接到下栅极线和下数据线的薄膜晶体管(“TFT”),设置在下栅极线上的绝缘层, 下数据线和TFT,并且具有暴露下栅极线和下数据线的多个沟槽,设置在下栅极线上的沟槽中的上栅极线,设置在下数据上的沟槽中的上数据线 线和与TFT连接的像素电极。

    THIN FILM TRANSISTOR DISPLAY PANEL AND MANUFACTURING METHOD THEREOF
    6.
    发明申请
    THIN FILM TRANSISTOR DISPLAY PANEL AND MANUFACTURING METHOD THEREOF 有权
    薄膜晶体管显示面板及其制造方法

    公开(公告)号:US20140024157A1

    公开(公告)日:2014-01-23

    申请号:US14036668

    申请日:2013-09-25

    Abstract: A thin film transistor display panel includes a substrate, a gate wire on the substrate and including a gate line and a gate electrode; a gate insulating layer on the gate wire; a semiconductor layer on the gate insulating layer; a data wire including a source electrode on the semiconductor layer, a drain electrode opposing the source electrode with respect to the gate electrode, and a data line; a passivation layer on the data wire having a contact hole exposing the drain electrode; and a pixel electrode on the passivation layer and connected to the drain electrode through the contact hole. The gate wire has a first region and second region where the gate line and the gate electrode are positioned, respectively. The thickness of the gate wire in the first region is greater than the thickness of the gate wire in the second region.

    Abstract translation: 薄膜晶体管显示面板包括衬底,衬底上的栅极线,并且包括栅极线和栅电极; 栅极线上的栅极绝缘层; 栅极绝缘层上的半导体层; 数据线,包括半导体层上的源电极,与源电极相对于栅电极相对的漏电极和数据线; 数据线上的钝化层具有暴露漏电极的接触孔; 以及钝化层上的像素电极,并通过接触孔与漏电极连接。 栅极线分别具有栅极线和栅电极所在的第一区域和第二区域。 第一区域中的栅极线的厚度大于第二区域中的栅极线的厚度。

    Thin film transistor substrate and display panel having the same
    7.
    发明授权
    Thin film transistor substrate and display panel having the same 有权
    薄膜晶体管基板和具有该薄膜晶体管基板的显示面板

    公开(公告)号:US09405163B2

    公开(公告)日:2016-08-02

    申请号:US14664189

    申请日:2015-03-20

    Abstract: A thin film transistor substrate includes a base substrate and a thin film transistor. The base substrate includes a gate line and a data line. The thin film transistor is connected to the gate line and the data line. The thin film transistor includes a gate electrode, a semiconductor pattern and source, drain electrodes. The gate electrode is disposed on the base substrate. The semiconductor pattern overlaps with the gate electrode. The source, drain electrodes is spaced apart from each other. The source electrode includes a first source layer, a second source layer disposed on the first source layer and a first diffusion barrier disposed between the first source layer and second source layer. The drain electrode includes a first drain layer, a second drain layer disposed on the first drain layer and a second diffusion barrier disposed between the first drain layer and second drain layer.

    Abstract translation: 薄膜晶体管基板包括基底基板和薄膜晶体管。 基板包括栅极线和数据线。 薄膜晶体管连接到栅极线和数据线。 薄膜晶体管包括栅电极,半导体图案和源极,漏极电极。 栅电极设置在基底基板上。 半导体图案与栅电极重叠。 源极,漏极彼此间隔开。 源电极包括第一源极层,设置在第一源极层上的第二源极层和设置在第一源极层和第二源极层之间的第一扩散阻挡层。 漏极包括第一漏极层,设置在第一漏极层上的第二漏极层和设置在第一漏极层和第二漏极层之间的第二扩散阻挡层。

    Thin film transistor array panel and method for manufacturing the same
    9.
    发明授权
    Thin film transistor array panel and method for manufacturing the same 有权
    薄膜晶体管阵列面板及其制造方法

    公开(公告)号:US09171999B2

    公开(公告)日:2015-10-27

    申请号:US13907132

    申请日:2013-05-31

    CPC classification number: H01L33/16 H01L27/124 H01L27/1288

    Abstract: A thin film transistor array panel is provided and includes a gate line, a gate insulating layer covering the gate line, a semiconductor layer disposed on the gate insulating layer, and a data line and a drain electrode disposed on the semiconductor layer. The data line and the drain electrode have a dual-layered structure including a lower layer and an upper layer with the lower layer having a first portion protruded outside the upper layer and the semiconductor layer having a second portion protruded outside the edge of the lower layer.

    Abstract translation: 提供了一种薄膜晶体管阵列面板,包括栅极线,覆盖栅极线的栅极绝缘层,设置在栅极绝缘层上的半导体层,以及设置在半导体层上的数据线和漏电极。 数据线和漏电极具有包括下层和上层的双层结构,其中下层具有突出于上层之外的第一部分,并且半导体层具有突出于下层边缘外侧的第二部分 。

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