Abstract:
A liquid crystal display apparatus includes a plurality of pixels having first and second subpixels, a plurality of gate lines connected to the first and second subpixels to transmit gate signals, a plurality of first data lines intersecting the gate lines and connected to the first subpixels to transmit first data voltages, and a plurality of second data lines intersecting the gate lines and connected to the second subpixels to transmit second data voltages. The first and second data voltages have different sizes and are obtained from single image information. Each pixel is divided into a pair of subpixels, and different data voltages are applied to the subpixels through two different data lines, so that it is possible to secure a wide viewing angle and improve side visibility.
Abstract:
A liquid crystal display according to an exemplary embodiment of the present invention includes: a first substrate and an opposing second substrate; a first pixel electrode and a second pixel electrode disposed in a pixel area, on the first substrate, and including a plurality of branch electrodes; and a liquid crystal layer interposed between the first and second electrodes. Branches electrode of the first pixel electrode and the second pixel electrode are interlaced. The first pixel electrode has an extension disposed adjacent to the center of the pixel area, and a minimum distance between the extension and the adjacent branch electrode is different from an average minimum between the adjacent branch electrodes.
Abstract:
A thin film transistor array panel is provided and includes a gate line, a gate insulating layer covering the gate line, a semiconductor layer disposed on the gate insulating layer, and a data line and a drain electrode disposed on the semiconductor layer. The data line and the drain electrode have a dual-layered structure including a lower layer and an upper layer with the lower layer having a first portion protruded outside the upper layer and the semiconductor layer having a second portion protruded outside the edge of the lower layer.
Abstract:
Provided is a thin film transistor array panel. The thin film transistor array panel includes: an insulation substrate including a display area with a plurality of pixels and a peripheral area around the display area; a gate line and a data line positioned in the display area of the insulation substrate; a first driving signal transfer line and a second driving signal transfer line positioned in the peripheral area of the insulation substrate; a first insulating layer positioned on the gate line and the data line; and a first photosensitive film positioned on the first driving signal transfer line and the second driving signal transfer line, in which the first photosensitive film is disposed only in the peripheral area.
Abstract:
Provided is a thin film transistor array panel. The thin film transistor array panel includes: an insulation substrate including a display area with a plurality of pixels and a peripheral area around the display area; a gate line and a data line positioned in the display area of the insulation substrate; a first driving signal transfer line and a second driving signal transfer line positioned in the peripheral area of the insulation substrate; a first insulating layer positioned on the gate line and the data line; and a first photosensitive film positioned on the first driving signal transfer line and the second driving signal transfer line, in which the first photosensitive film is disposed only in the peripheral area.
Abstract:
A display panel includes a first substrate including a switching device array, a second substrate spaced apart from the first substrate, a column spacer maintaining a cell gap between the first substrate and the second substrate, the first substrate includes a gate line on a base substrate and extending in a direction, a data line crossing with the gate line, a switching device electrically connected to the gate line and the data line and including a gate electrode, a source electrode and a drain electrode, a pixel electrode connected to the switching device and a dummy pattern adjacent to the column spacer.
Abstract:
A display apparatus includes a display panel comprising a plurality of pixels, each of the pixels comprising a thin film transistor connected to a gate line and a data line and a display element connected to the thin film transistor, a driving voltage generator configured to generate a gate-on voltage and a plurality of gate-off voltages, a timing controller configured to divide an initial driving period into a plurality of setting periods and output a gate-off voltage corresponding to each of the setting periods, and a gate driver circuit configured to generate a gate signal using the gate-on voltage and the gate-off voltage corresponding to a setting period and output the gate signal to the gate line.
Abstract:
A display panel includes a first substrate including a switching device array, a second substrate spaced apart from the first substrate, a column spacer maintaining a cell gap between the first substrate and the second substrate, the first substrate includes a gate line on a base substrate and extending in a direction, a data line crossing with the gate line, a switching device electrically connected to the gate line and the data line and including a gate electrode, a source electrode and a drain electrode, a pixel electrode connected to the switching device and a dummy pattern adjacent to the column spacer.
Abstract:
Provided is a thin film transistor array panel. The thin film transistor array panel includes: an insulation substrate including a display area with a plurality of pixels and a peripheral area around the display area; a gate line and a data line positioned in the display area of the insulation substrate; a first driving signal transfer line and a second driving signal transfer line positioned in the peripheral area of the insulation substrate; a first insulating layer positioned on the gate line and the data line; and a first photosensitive film positioned on the first driving signal transfer line and the second driving signal transfer line, in which the first photosensitive film is disposed only in the peripheral area.
Abstract:
Provided is a thin film transistor array panel. The thin film transistor array panel includes: an insulation substrate including a display area with a plurality of pixels and a peripheral area around the display area; a gate line and a data line positioned in the display area of the insulation substrate; a first driving signal transfer line and a second driving signal transfer line positioned in the peripheral area of the insulation substrate; a first insulating layer positioned on the gate line and the data line; and a first photosensitive film positioned on the first driving signal transfer line and the second driving signal transfer line, in which the first photosensitive film is disposed only in the peripheral area.