公开(公告)号：US10164082B2

公开(公告)日：2018-12-25

申请号：US15466461

申请日：2017-03-22

Applicant: STC.UNM

Inventor： Steven R. J. Brueck ,  Seung-Chang Lee ,  Christian Wetzel ,  Mark Durniak

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66 ,  H01L29/205 ,  H01L29/08 ,  H01L21/78 ,  H01L29/04 ,  H01L29/423 ,  H01L29/06 ,  H01L33/00 ,  H01L33/32 ,  H01L29/40 ,  H01L33/24

Abstract: A transistor comprises a substrate comprising a Group III/V compound semiconductor material having a cubic crystalline phase structure positioned on a hexagonal crystalline phase layer having a first region and a second region, the cubic crystalline phase structure being positioned between the first region and the second region of the hexagonal crystalline phase layer. A source region and a drain region are both positioned in the Group III/V compound semiconductor material. A channel region is in the Group III/V compound semiconductor material. A gate is over the channel region. An optional backside contact can also be formed. A source contact and electrode are positioned to provide electrical contact to the source region. A drain contact and electrode are positioned to provide electrical contact to the drain region. Methods of forming transistors are also disclosed.

公开(公告)号：US09766123B2

公开(公告)日：2017-09-19

申请号：US15317592

申请日：2015-06-09

Applicant: STC.UNM

Inventor： Steven R. J. Brueck ,  Alexander Neumann ,  Payman Zarkesh-Ha

IPC: G01J5/02 ,  G01J1/06 ,  G01J3/28 ,  G01J3/18 ,  G01J1/44 ,  H01L27/144 ,  H01L31/0232 ,  H01L31/103 ,  H01L31/02 ,  H01L31/0216 ,  G02B6/122 ,  G02B6/12 ,  G02B6/124

CPC classification number: G01J1/06 ,  G01J1/44 ,  G01J3/0218 ,  G01J3/0259 ,  G01J3/18 ,  G01J3/1895 ,  G01J3/2803 ,  G01J2001/448 ,  G02B6/12004 ,  G02B6/122 ,  G02B6/124 ,  G02B2006/12061 ,  G02B2006/12107 ,  G02B2006/12138 ,  H01L27/1446 ,  H01L31/02019 ,  H01L31/02164 ,  H01L31/02327 ,  H01L31/103

Abstract: A 2-D sensor array includes a semiconductor substrate and a plurality of pixels disposed on the semiconductor substrate. Each pixel includes a coupling region and a junction region, and a slab waveguide structure disposed on the semiconductor substrate and extending from the coupling region to the region. The slab waveguide includes a confinement layer disposed between a first cladding layer and a second cladding layer. The first cladding and the second cladding each have a refractive index that is lower than a refractive index of the confinement layer. Each pixel also includes a coupling structure disposed in the coupling region and within the slab waveguide. The coupling structure includes two materials having different indices of refraction arranged as a grating defined by a grating period. The junction region comprises a p-n junction in communication with electrical contacts for biasing and collection of carriers resulting from absorption of incident radiation.

公开(公告)号：US09142400B1

公开(公告)日：2015-09-22

申请号：US13944808

申请日：2013-07-17

Applicant: STC.UNM

Inventor： Steven R. J. Brueck ,  Stephen D. Hersee ,  Seung-Chang Lee ,  Daniel Feezell

IPC: H01L29/06 ,  H01L21/02 ,  H01L27/12

CPC classification number: H01L21/02107 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02639 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66469 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7783 ,  H01L29/785

Abstract: A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.

Abstract translation: 一种制造异质外延层的方法。 该方法包括提供半导体衬底。 在半导体衬底上形成用选择性生长掩模描绘的种子区域。 种子区域包括第一材料并且具有小于100nm的线性表面尺寸。 在种子区域上生长异质外延层，异质外延层包含不同于第一材料的第二材料。 还公开了通过该方法制造的器件。

公开(公告)号：US10483105B2

公开(公告)日：2019-11-19

申请号：US15573772

申请日：2016-05-13

Applicant: STC.UNM

Inventor： Seung-Chang Lee ,  Steven R. J. Brueck

IPC: H01L21/02 ,  B81C1/00 ,  B82Y10/00 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L27/092 ,  H01L29/786 ,  H01L29/06 ,  H01L21/285 ,  H01L21/306 ,  H01L21/311 ,  B82Y40/00

Abstract: Provided is a method for growing a nanowire, including: providing a substrate with a base portion having a first surface and at least one support structure extending above or below the first surface; forming a dielectric coating on the at least one support structure; forming a photoresist coating over the substrate; forming a metal coating over at least a portion of the dielectric coating; removing a portion of the dielectric coating to expose a surface of the at least one support structure; removing a portion of the at least one support structure to form a nanowire growth surface; growing at least one nanowire on the nanowire growth surface of a corresponding one of the at least one support structure, wherein the nanowire comprises a root end attached to the growth surface and an opposing, free end extending from the root end; and elastically bending the at least one nanowire.

公开(公告)号：US09153431B1

公开(公告)日：2015-10-06

申请号：US13670391

申请日：2012-11-06

Applicant: STC.UNM

Inventor： Seung-Chang Lee ,  Steven R. J. Brueck

IPC: H01L21/02 ,  H01L29/06

CPC classification number: C30B25/04 ,  C30B25/18 ,  C30B25/186 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/02647 ,  H01L27/1222 ,  H01L29/045 ,  H01L29/06 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/2003

Abstract: A method of epitaxially growing nitrogen-based compound semiconductor thin films on a semiconductor substrate, which is periodically patterned with grooves. The method can provide an epitaxial growth of a first crystalline phase epitaxial film on the substrate, and block the growth of an initial crystalline phase with barrier materials prepared at the sides of the grooves. Semiconductor devices employing the epitaxial films are also disclosed.

Abstract translation: 在半导体衬底上外延生长氮基化合物半导体薄膜的方法，该半导体衬底周期性地形成凹槽。 该方法可以在衬底上提供第一结晶相外延膜的外延生长，并且阻挡初始结晶相的生长与在槽的侧面制备的阻挡材料的生长。 还公开了使用外延膜的半导体器件。

公开(公告)号：US08785226B2

公开(公告)日：2014-07-22

申请号：US14032904

申请日：2013-09-20

Applicant: STC.UNM

Inventor： Seung Chang Lee ,  Steven R. J. Brueck

IPC: H01S5/10 ,  H01S5/323 ,  H01S5/343 ,  H01L21/00

CPC classification number: H01L21/02603 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02507 ,  H01L21/02521 ,  H01L21/02639 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/127 ,  H01L29/158 ,  H01L29/7783 ,  H01L29/7853 ,  H01L33/06 ,  H01L33/18 ,  H01S5/32 ,  Y10S977/951 ,  Y10S977/962

Abstract: Exemplary embodiments provide semiconductor nanowires and nanowire devices/applications and methods for their formation. In embodiments, in-plane nanowires can be epitaxially grown on a patterned substrate, which are more favorable than vertical ones for device processing and three-dimensional (3D) integrated circuits. In embodiments, the in-plane nanowire can be formed by selective epitaxy utilizing lateral overgrowth and faceting of an epilayer initially grown in a one-dimensional (1D) nanoscale opening. In embodiments, optical, electrical, and thermal connections can be established and controlled between the nanowire, the substrate, and additional electrical or optical components for better device and system performance.

Abstract translation: 示例性实施例提供用于其形成的半导体纳米线和纳米线器件/应用和方法。 在实施例中，平面内纳米线可以在图案化衬底上外延生长，其比用于器件处理和三维（3D）集成电路的垂直纳米线更有利。 在实施方案中，可以通过使用最初在一维（1D）纳米尺度开口中生长的外延层的横向过生长和刻面的选择性外延来形成平面内纳米线。 在实施例中，可以在纳米线，衬底和附加电气或光学部件之间建立和控制光学，电气和热连接，以获得更好的器件和系统性能。

公开(公告)号：US09617590B2

公开(公告)日：2017-04-11

申请号：US14347690

申请日：2012-09-28

Applicant: STC.UNM

Inventor： Jeremy Edwards ,  Payman Zarkesh-Ha ,  Steven R. J. Brueck

IPC: C12Q1/68 ,  G01N27/414

CPC classification number: C12Q1/6869 ,  C12Q1/6806 ,  C12Q1/6874 ,  G01N27/414 ,  G01N27/4145 ,  Y10T436/143333 ,  C12Q2531/125 ,  C12Q2535/122

Abstract: This disclosure describes, in one aspect, a method for preparing DNA molecule for sequencing. Generally, the method includes fragmenting the DNA molecule into double-stranded fragments; amplifying at least a portion of the double-stranded fragments; circularizing the fragments so that the first end of the fragment comprises a first loop connecting the strands and the second end of the fragment comprises a second loop connecting the strands; annealing a first sequencing primer to the first loop oriented to sequence at least a portion of one strand of the fragment; and annealing a second sequencing primer to the second loop oriented to sequence at least a portion of the other strand of the fragment. In another aspect, this disclosure describes a method for sequencing a DNA molecule. Generally, the method includes fragmenting the DNA molecule into double-stranded fragments; amplifying at least a portion of the double-stranded fragments; circularizing the fragments so that the first end of the fragment comprises a first loop connecting the strands and the second end of the fragment comprises a second loop connecting the strands; and sequencing at least one of the DNA strands.

公开(公告)号：US09520472B2

公开(公告)日：2016-12-13

申请号：US14383833

申请日：2013-03-15

Applicant: STC.UNM

Inventor： Steven R. J. Brueck ,  Seung-Chang Lee ,  Christian Wetzel ,  Theeradetch Detchprohm ,  Christoph Stark

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/20 ,  H01L33/16 ,  H01L33/24 ,  H01L29/15

CPC classification number: H01L29/2003 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02587 ,  H01L21/02598 ,  H01L21/02658 ,  H01L29/15 ,  H01L33/16 ,  H01L33/24

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate comprising a groove. A buffer layer is formed on a surface of the groove. The buffer layer comprising at least one material chosen from AIN, GaN or AlxGa1-xN, where x is between zero and one. An epitaxially grown semiconductor material is disposed over the buffer layer, at least a portion of the epitaxially grown semiconductor material having a cubic crystalline phase structure. Methods of forming the semiconductor devices are also taught.

Abstract translation: 公开了一种半导体器件。 半导体器件包括包括沟槽的衬底。 在槽的表面上形成缓冲层。 所述缓冲层包含至少一种选自AIN，GaN或Al x Ga 1-x N的材料，其中x在0和1之间。 外延生长的半导体材料设置在缓冲层之上，至少部分外延生长的半导体材料具有立方晶相结构。 还教导了形成半导体器件的方法。

公开(公告)号：US10453996B2

公开(公告)日：2019-10-22

申请号：US15374547

申请日：2016-12-09

Applicant: STC.UNM

Inventor： Steven R. J. Brueck ,  Seung-Chang Lee ,  Christian Wetzel ,  Mark Durniak

IPC: H01L29/778 ,  H01L33/32 ,  H01L21/02 ,  H01L21/78 ,  H01L33/00 ,  H01L33/04 ,  H01L33/18 ,  H01L29/04

Abstract: A method of forming a semiconductor structure includes providing a substrate comprising a first material portion and a single crystal silicon layer on the first material portion. The substrate further comprises a major front surface, a major backside surface opposing the major front surface, and a plurality of grooves positioned in the major front surface. A buffer layer is deposited in one or more of the plurality of grooves. A semiconductor material is epitaxially grown over the buffer layer and in the one or more plurality of grooves, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase.

公开(公告)号：US10411436B2

公开(公告)日：2019-09-10

申请号：US15571800

申请日：2016-05-06

Applicant: STC.UNM

Inventor： Steven R. J. Brueck ,  Sanjay Krishna ,  Daniel P. Dapkus

IPC: H01S5/00 ,  H01S5/12 ,  H01S5/042 ,  H01S5/026 ,  H01S5/02 ,  H01S5/022 ,  H01S5/04 ,  H01S5/40 ,  H01S3/13 ,  H01S5/50 ,  H01S5/343 ,  G01N21/17 ,  G01N21/39

Abstract: A tunable laser device includes a laser structure and a plurality of individually addressable, separated contact stripes disposed on the laser structure. The laser structure includes a substrate, an active portion disposed on the substrate, and a chirped distributed feedback (DFB) grating disposed on the active portion. The active portion includes at least top and bottom contact layers and a gain medium.