公开(公告)号：US20150262841A1

公开(公告)日：2015-09-17

申请号：US14568603

申请日：2014-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee Jeong KIM ,  Yong Kwan LEE

IPC: H01L21/48 ,  H05K3/06 ,  H01L25/00 ,  H01L25/065 ,  H01L21/52 ,  H01L23/00

CPC classification number: H05K3/06 ,  H01L21/486 ,  H01L21/52 ,  H01L23/13 ,  H01L23/145 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/43 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/29036 ,  H01L2224/32135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48106 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/49176 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/152 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H05K1/144 ,  H05K1/183 ,  H05K3/4697 ,  H05K2201/041 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/48227 ,  H01L2924/00012

Abstract: A method of manufacturing a circuit board may include: preparing a circuit board body including an insulating layer having a first surface and a second surface opposite to the first surface and a first conductive thin film layer disposed on the first surface of the insulating layer and having a convex portion which is disposed on a first surface of the first conductive thin film layer and is embedded in the insulating layer; removing the convex portion to form a cavity corresponding to the convex portion in the insulating layer; and forming one or more first wiring patterns on the first surface of the insulating layer by removing first portions of the first conductive thin film layer. The one or more first wiring patterns correspond to second portions of the first conductive thin film layer not removed.

Abstract translation: 制造电路板的方法可以包括：制备电路板主体，其包括具有第一表面和与第一表面相对的第二表面的绝缘层，以及设置在绝缘层的第一表面上的第一导电薄膜层，并且具有 凸部，其设置在所述第一导电性薄膜层的第一表面上并嵌入所述绝缘层中; 去除所述凸部以形成与所述绝缘层中的所述凸部对应的空腔; 以及通过去除第一导电薄膜层的第一部分，在绝缘层的第一表面上形成一个或多个第一布线图案。 一个或多个第一布线图案对应于未被去除的第一导电薄膜层的第二部分。

公开(公告)号：US20210391199A1

公开(公告)日：2021-12-16

申请号：US17200981

申请日：2021-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Young OH ,  Seung Hwan KIM ,  Jong Ho PARK ,  Yong Kwan LEE ,  Jong Ho LEE

IPC: H01L21/673

Abstract: The present disclosure provides a magazine supporting equipment for supporting a magazine with multiple input ports. The magazine supporting equipment comprises a contact plate, a first sidewall plate, and a second sidewall plate. The contact plate is in contact with the magazine. The first sidewall plate extends vertically from one end of the contact plate. The second sidewall plate parallel is to the first sidewall plate and extends vertically from one end to the other end of the contact plate. The first sidewall plate extends along at least a part of a first sidewall of the magazine. The second sidewall plate extends along at least a part of a second sidewall of the magazine. The first sidewall plate and the second sidewall plate include control openings through which gas flows in and out.

公开(公告)号：US20210320067A1

公开(公告)日：2021-10-14

申请号：US17035000

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Joo KIM ,  Sun Chul KIM ,  Min Keun KWAK ,  Hyun Ki KIM ,  Hyung Gil BAEK ,  Yong Kwan LEE

IPC: H01L23/538 ,  H01L25/10 ,  H01L25/18 ,  H01L21/48 ,  H01L23/498

Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.

公开(公告)号：US20220392845A1

公开(公告)日：2022-12-08

申请号：US17891190

申请日：2022-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Joo KIM ,  Sun Chul KIM ,  Min Keun KWAK ,  Hyun Ki KIM ,  Hyung Gil BAEK ,  Yong Kwan LEE

IPC: H01L23/538 ,  H01L25/10 ,  H01L25/18 ,  H01L21/48 ,  H01L23/498

Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.

公开(公告)号：US20190363073A1

公开(公告)日：2019-11-28

申请号：US16167173

申请日：2018-10-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Gi HONG ,  Yong Kwan LEE

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L23/18

Abstract: A semiconductor device package-on-package (PoP) includes a first package, a second package, an interposer, a first molding layer, and a second molding layer. The first package includes a first substrate and a first semiconductor chip on the first substrate. The second package is disposed on the first package and includes a second substrate and a second semiconductor chip on the second substrate. The interposer is disposed between the first package and the second package and connects the first package and the second package. A first molding layer fills a space between the first package and the interposer. A second molding layer covers an upper surface of the interposer.