公开(公告)号：US20240128239A1

公开(公告)日：2024-04-18

申请号：US18471875

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Solji SONG ,  Junyun KWEON ,  Byeongchan KIM ,  Jumyong PARK ,  Dongjoon OH ,  Hyunchul JUNG ,  Hyunsu HWANG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/08145 ,  H01L2224/16227

Abstract: A semiconductor package includes a connection structure, a via protection layer on the connection structure, a first semiconductor chip on the via protection layer and including a first substrate having a first active face and a first inactive face opposite to each other a through-silicon via (TSV) configured to electrically connect the first semiconductor chip to the connection structure, and a second semiconductor chip on the first semiconductor chip and electrically connected to the first semiconductor chip. The second semiconductor chip includes a second substrate having a second active face and a second inactive face opposite to each other. The package includes a conductive post configured to electrically connect the second semiconductor chip and the connection structure with each other, and a molding layer filling a space between an upper surface of the connection structure and the second semiconductor chip, and the molding layer encloses the conductive post.

公开(公告)号：US20220059466A1

公开(公告)日：2022-02-24

申请号：US17198359

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Solji SONG ,  Byeongchan KIM ,  Jumyong PARK ,  Jinho AN ,  Chungsun LEE ,  Jeonggi JIN ,  Juil CHOI

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes an interposer having a first surface and a second surface opposite to the first surface and including a plurality of bonding pads, and first and second semiconductor devices on the interposer. Each of the plurality of bonding pads includes a first pad pattern provided to be exposed from the first surface and having a first width and a second pad pattern provided on the first pad pattern and having a second width greater than the first width.

公开(公告)号：US20240030169A1

公开(公告)日：2024-01-25

申请号：US18116414

申请日：2023-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woon Chun KIM ,  Dae Seo PARK ,  Jumyong PARK

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L24/03 ,  H01L2224/05073 ,  H01L2224/05018 ,  H01L2224/05026 ,  H01L2224/05144 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05571 ,  H01L2224/05562 ,  H01L2224/05647 ,  H01L2224/05082 ,  H01L2224/08145 ,  H01L2224/80013 ,  H01L2224/80004 ,  H01L2224/80379 ,  H01L2924/0544 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/0346 ,  H01L2224/03845 ,  H01L2224/0345 ,  H01L2224/0384 ,  H01L2224/8002

Abstract: A semiconductor device includes a lower structure and an upper structure on the lower structure. The lower structure includes a first semiconductor substrate, a first pad and a first dielectric layer. The first dielectric layer surrounds the first pad and exposes a top surface of the first pad. The upper structure includes a second semiconductor substrate, a second pad and a second dielectric layer. The second dielectric layer surrounds the second pad and exposes a bottom surface of the second pad. The first pad and the second pad are bonded to each other across an interfacial layer to couple the upper and lower structures to each other. The first and second pads and the interfacial layer include a same metallic material. The first and second pads have a substantially same average grain size and the interfacial layer has a different average grain size than the first and second pads.

公开(公告)号：US20220059442A1

公开(公告)日：2022-02-24

申请号：US17230511

申请日：2021-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjoon OH ,  Junyun KWEON ,  Jumyong PARK ,  Jin Ho AN ,  Chungsun LEE ,  Hyunsu HWANG

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538

Abstract: Disclosed are interconnection structures and semiconductor packages. The interconnection structure includes a first dielectric layer and a first hardmask pattern that are sequentially stacked, and a first interconnection pattern that penetrates the first hardmask pattern and the first dielectric layer. The first hardmask pattern includes a dielectric material having an etch selectivity with respect to the first dielectric layer. The first interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other. The first pad part vertically overlaps the via part. The line part extends from the first pad part. A level of a bottom surface of the first pad part is lower than a level of a bottom surface of the line part.

公开(公告)号：US20150068948A1

公开(公告)日：2015-03-12

申请号：US14281880

申请日：2014-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi Koan HONG ,  Byung Lyul PARK ,  Jumyong PARK ,  Jisoon PARK ,  Kyu-Ha LEE ,  Siyoung CHOI

IPC: H01L21/673

CPC classification number: H01L21/6733 ,  H01L21/6732 ,  H01L21/67323 ,  H01L21/67326

Abstract: Embodiments of the present inventive concepts provide a wafer loader having one or more buffer zones to prevent damage to a wafer loaded in the wafer loader. The wafer loader may include a plurality of loading sections that protrude from a main body and are configured to be arranged at various locations along an edge of the wafer. Each of the loading sections may include a groove into which the edge of the wafer may be inserted. The loading section may include first and second protrusions having first and second inner sides, respectively, that face each other to define the groove therebetween. At least one of the first and second inner sides may include a recess to define the buffer zone.

Abstract translation: 本发明构思的实施例提供了具有一个或多个缓冲区的晶片装载器，以防止损坏装载在晶片装载器中的晶片。 晶片装载机可以包括从主体突出的多个装载部分，并被构造成沿着晶片的边缘布置在不同位置。 每个加载部分可以包括槽，其中可以插入晶片的边缘。 装载部分可以包括分别具有彼此面对以限定其间的凹槽的第一和第二内侧的第一和第二突起。 第一和第二内侧中的至少一个可以包括限定缓冲区的凹部。

公开(公告)号：US20240312923A1

公开(公告)日：2024-09-19

申请号：US18677075

申请日：2024-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Solji SONG ,  Byeongchan KIM ,  Jumyong PARK ,  Jinho AN ,  Chungsun LEE ,  Jeonggi JIN ,  Juil CHOI

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227

Abstract: A semiconductor package includes an interposer having a first surface and a second surface opposite to the first surface and including a plurality of bonding pads, and first and second semiconductor devices on the interposer. Each of the plurality of bonding pads includes a first pad pattern provided to be exposed from the first surface and having a first width and a second pad pattern provided on the first pad pattern and having a second width greater than the first width.

公开(公告)号：US20230238316A1

公开(公告)日：2023-07-27

申请号：US18189834

申请日：2023-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il CHOI ,  Jumyong PARK ,  Jin Ho AN ,  Chungsun LEE ,  Teahwa JEONG ,  Jeonggi JIN

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L25/0652

Abstract: A method for manufacturing a semiconductor package may include: forming a photoimageable dielectric layer on a substrate including a pad; forming a preliminary via hole in the photoimageable dielectric layer to expose the pad; forming a hard mask layer on the photoimageable dielectric layer and the pad; etching the photoimageable dielectric layer and the hard mask layer to form a via hole, a first hole, and a trench; forming a metal layer on the photoimageable dielectric layer connected to the pad; planarizing the metal layer to form a wiring pattern; and placing a semiconductor chip electrically connected to the wiring pattern. The first hole may be disposed on the via hole and connected thereto, and a diameter of the first hole may be larger than a diameter of the via hole.

公开(公告)号：US20230111136A1

公开(公告)日：2023-04-13

申请号：US17966864

申请日：2022-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong PARK ,  Solji Song ,  Jinho AN ,  Jeonggi JIN ,  Jinho CHUN ,  Juil CHOI

IPC: H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768

Abstract: A semiconductor device is disclosed. The semiconductor device includes a via passivation layer disposed on an inactive surface of a substrate, a through-electrode vertically penetrating the substrate and the via passivation layer, a concave portion formed in the top surface of the via passivation layer and disposed adjacent to the through-electrode, and a via protective layer coplanar with the via passivation layer and the through-electrode and to fill the concave portion. In a horizontal cross-sectional view, the via protective layer has a band shape surrounding the through-electrode.

公开(公告)号：US20250105181A1

公开(公告)日：2025-03-27

申请号：US18975625

申请日：2024-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong PARK ,  Unbyoung KANG ,  Byeongchan KIM ,  Solji SONG ,  Chungsun LEE

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip having a first substrate, a first insulating layer on the first substrate, and a plurality of first bonding pads on the first insulating layer, and having a flat upper surface by an upper surface of the first insulating layer and upper surfaces of the plurality of first bonding pads; and a second semiconductor chip on the upper surface of the first semiconductor chip and having a second substrate, a second insulating layer below the second substrate and in contact with the first insulating layer, and a plurality of second bonding pads on the second insulating layer and in contact with the first bonding pads, respectively, wherein the first insulating layer includes an insulating interfacial layer in contact with the second insulating layer, embedded in the first insulating layer, and spaced apart from the plurality of first bonding pads.

公开(公告)号：US20240290702A1

公开(公告)日：2024-08-29

申请号：US18655879

申请日：2024-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjoon OH ,  Junyun KWEON ,  Jumyong PARK ,  Jin Ho AN ,  Chungsun LEE ,  Hyunsu HWANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/3128 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16227

Abstract: Disclosed are interconnection structures and semiconductor packages. The interconnection structure includes a first dielectric layer and a first hardmask pattern that are sequentially stacked, and a first interconnection pattern that penetrates the first hardmask pattern and the first dielectric layer. The first hardmask pattern includes a dielectric material having an etch selectivity with respect to the first dielectric layer. The first interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other. The first pad part vertically overlaps the via part. The line part extends from the first pad part. A level of a bottom surface of the first pad part is lower than a level of a bottom surface of the line part.