公开(公告)号：US20240030169A1

公开(公告)日：2024-01-25

申请号：US18116414

申请日：2023-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woon Chun KIM ,  Dae Seo PARK ,  Jumyong PARK

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L24/03 ,  H01L2224/05073 ,  H01L2224/05018 ,  H01L2224/05026 ,  H01L2224/05144 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05571 ,  H01L2224/05562 ,  H01L2224/05647 ,  H01L2224/05082 ,  H01L2224/08145 ,  H01L2224/80013 ,  H01L2224/80004 ,  H01L2224/80379 ,  H01L2924/0544 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/0346 ,  H01L2224/03845 ,  H01L2224/0345 ,  H01L2224/0384 ,  H01L2224/8002

Abstract: A semiconductor device includes a lower structure and an upper structure on the lower structure. The lower structure includes a first semiconductor substrate, a first pad and a first dielectric layer. The first dielectric layer surrounds the first pad and exposes a top surface of the first pad. The upper structure includes a second semiconductor substrate, a second pad and a second dielectric layer. The second dielectric layer surrounds the second pad and exposes a bottom surface of the second pad. The first pad and the second pad are bonded to each other across an interfacial layer to couple the upper and lower structures to each other. The first and second pads and the interfacial layer include a same metallic material. The first and second pads have a substantially same average grain size and the interfacial layer has a different average grain size than the first and second pads.

公开(公告)号：US20240332245A1

公开(公告)日：2024-10-03

申请号：US18610924

申请日：2024-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Seo PARK ,  Woon Chun KIM

IPC: H01L23/00

CPC classification number: H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/751 ,  H01L2224/75301 ,  H01L2224/7555 ,  H01L2224/81203 ,  H01L2224/83203 ,  H01L2224/9211

Abstract: The present disclosure relates to a semiconductor chip bonding device and a semiconductor chip bonding method using the same, the semiconductor chip bonding device bonds semiconductor chips on a substrate, and includes a bonding head disposed on the semiconductor chip; a substrate support disposed below the substrate; a dam member for surrounding an edge of the bonding head and contacting an upper side of the substrate; and a gas blower spaced and disposed on the substrate support, disposed between the bonding head and the dam member, and supplying gas to the substrate direction.

公开(公告)号：US20200152580A1

公开(公告)日：2020-05-14

申请号：US16403968

申请日：2019-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woon Chun KIM ,  Jun Heyoung PARK ,  Ji Hye SHIM ,  Sung Keun PARK ,  Gun LEE

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor package includes a connection structure including one or more redistribution layers, a semiconductor chip disposed on the connection structure and electrically connected to the one or more redistribution layers, an encapsulant disposed on the connection structure and covering at least a portion of the semiconductor chip, and a shielding structure covering at least a portion of the encapsulant. The shielding structure includes a conductive pattern layer having a plurality of openings, a first metal layer covering the conductive pattern layer and extending across the plurality of openings, and a second metal layer covering the first metal layer. The second metal layer has a thickness greater than a thickness of the first metal layer.