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    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220262810A1

    公开(公告)日：2022-08-18

    申请号：US17737164

    申请日：2022-05-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JANGGN YUN ,  JAEDUK LEE

    IPC: H01L27/11548 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11519 ,  H01L27/11565 ,  H01L23/522

    Abstract: A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes stacked on the substrate, a channel structure penetrating the plurality of gate electrodes and including a channel layer extending in a vertical direction perpendicular to an upper surface of the substrate in the memory cell region, a dummy channel structure penetrating the plurality of gate electrodes and including a dummy channel layer extending in the vertical direction in the connection region, a first semiconductor layer disposed between the substrate and a lowermost one of the plurality of gate electrodes and surrounding the channel structure in the memory cell region, and an insulating separation structure disposed between the substrate and the lowermost one of the plurality of gate electrodes and surrounding the dummy channel layer.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开
    三维半导体存储器件

    公开(公告)号：US20170062453A1

    公开(公告)日：2017-03-02

    申请号：US15348009

    申请日：2016-11-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YUNGHWAN SON ,  JAESUNG SIM ,  SHINHWAN KANG ,  YOUNGWOO PARK ,  JAEDUK LEE

    IPC: H01L27/115

    CPC classification number: H01L27/11575 ,  G11C5/025 ,  G11C16/0483 ,  G11C16/30 ,  H01L27/11517 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/34

    Abstract: A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.

    Abstract translation: 一种三维（3D）半导体存储器件，其包括外围逻辑结构，该外围逻辑结构包括设置在半导体衬底上的外围逻辑电路和与外围逻辑电路重叠的第一绝缘层，以及在周边彼此间隔开的多个存储块 逻辑结构。 存储块中的至少一个包括阱板电极，与阱板电极的第一表面接触的半导体层，包括垂直堆叠在半导体层上的多个电极的堆叠结构，以及多个垂直结构穿透 堆叠结构并连接到半导体层。

    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250022798A1

    公开(公告)日：2025-01-16

    申请号：US18441071

    申请日：2024-02-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： HAKSEON KIM ,  DONGJIN LEE ,  JAEDUK LEE ,  KANG-OH YUN

    IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

    Abstract: According to an aspect of the present disclosure, a semiconductor device includes a peripheral structure, and a cell structure stacked on the peripheral structure. The cell structure includes a first substrate including a pad region and a cell region including a cell array region and an extending region, wherein the first substrate includes a first surface and a second surface opposite to the first surface, and wherein second surface faces the peripheral structure, a gate stacking structure including a plurality of gate electrodes and a plurality of interlayer insulating layers alternately stacked on the second surface of the first substrate, a channel structure disposed on the cell array region and penetrating the plurality of gate electrodes and the plurality of interlayer insulating layers, a plurality of gate contacts disposed on the extending region and connected to the plurality of gate electrodes, respectively, a cell insulation layer positioned over the second surface of the first substrate and covering the gate stacking structure, and an input/output contact disposed on the pad region and penetrating the cell insulation layer. The peripheral structure includes a second substrate electrically connected to the first substrate, a plurality of circuit elements positioned on the second substrate, a first barrier structure positioned over the second substrate and including a plurality of lower barrier layers, a plurality of first via holes disposed on the cell region and the pad region and penetrating at least one of the plurality of lower barrier layers, a plurality of second via holes disposed on the cell region and penetrating at least one of the plurality of lower barrier layers, and a plurality of contact vias positioned within the plurality of first via holes and connected to the plurality of circuit elements. In at least one lower barrier layer of the plurality of lower barrier layers, a sum of areas of at least one of the plurality of first via holes per unit area on the pad region is equal to a sum of areas of at least one of the plurality of first via holes on the cell region and areas of the plurality of second via holes per unit area on the cell region.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    5.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200328227A1

    公开(公告)日：2020-10-15

    申请号：US16787195

    申请日：2020-02-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JIN-KYU KANG ,  WOOJAE JANG ,  CHANGSUB LEE ,  SEJUN PARK ,  JAEDUK LEE ,  JUNG HOON LEE

    IPC: H01L27/11582 ,  H01L29/423 ,  H01L29/792

    Abstract: A three-dimensional semiconductor memory device including a stack structure including gate structures and first dielectric patterns alternately stacked, a vertical channel penetrating the stack structure, and a charge storage layer extending from between the vertical channel and the first gate structures to between the vertical channel and the first dielectric patterns. The gate structures include first gate structures having a top surface and a bottom surface facing each other and having different width. The charge storage layer includes first segments between the vertical channel and the first gate structures, and second segments between the vertical channel and the first dielectric patterns. A thickness of the first segments is greater than a thickness of the second segments. One of the width of the top surface and the width of bottom surface of each first gate structure is the same as that of a first dielectric pattern on the first gate structure.

    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20250048638A1

    公开(公告)日：2025-02-06

    申请号：US18432459

    申请日：2024-02-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HAKSEON KIM ,  KANG-OH YUN ,  DONGJIN LEE ,  YOUNGROK KIM ,  RYOONGBIN LEE ,  JAEDUK LEE

    IPC: H10B43/40 ,  G11C16/24 ,  H10B43/27

    Abstract: Disclosed are a semiconductor device and an electronic system including the semiconductor device. The semiconductor device includes a semiconductor substrate including a plurality of trenches and silicon, a gate electrode positioned on the semiconductor substrate and between the trenches, and a source region and a drain region respectively positioned within the trenches. The source region and the drain region include silicon carbide (SiC) or gallium nitride (GaN), the source region and the drain region each includes a first lightly doped region and a second lightly doped region, and a whole of the first lightly doped region overlaps the second lightly doped region in a direction perpendicular to an upper surface of the semiconductor substrate.

    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20230023911A1

    公开(公告)日：2023-01-26

    申请号：US17867962

    申请日：2022-07-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JAEDUK LEE ,  JOONAM KIM ,  SEJUN PARK ,  RAEYOUNG LEE

    IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

    Abstract: Semiconductor devices are provided. The semiconductor devices may include a peripheral circuit structure, a memory cell block arranged on the peripheral circuit structure and including strings, each of which includes a lower select transistor, memory cell transistors, and an upper select transistor connected in series and stacked in a vertical direction, and bit lines on the memory cell block. The bit lines may include a first bit line electrically connected to first to third strings of the strings. The lower select transistors of the first to third strings include first to third lower select gate electrodes, respectively. The second lower select gate electrode may be arranged at a different vertical level from the first lower select gate electrode, and the third lower select gate electrode may be arranged at the same vertical level as the first lower select gate electrode.

    SEMICONDUCTOR DEVICES
    10.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210343750A1

    公开(公告)日：2021-11-04

    申请号：US17154583

    申请日：2021-01-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： SOHYEON LEE ,  SUNGSU MOON ,  JAEDUK LEE ,  IKHYUNG JOO

    IPC: H01L27/12 ,  H01L21/84

    Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation film and providing a first channel region; a first source/drain region in the active region on first and second sides of the first channel region; a gate structure having a first gate insulating film, a shared gate electrode, and a second gate insulating film, sequentially arranged on the active region; a cover semiconductor layer on the second gate insulating film and electrically separated from the active region to provide a second channel region; a second source/drain. region in the cover semiconductor layer on first and second sides of the second channel region first and second source/drain contacts respectively connected to the first and second source/drain regions; and a shared gate contact connected to the shared gate electrode.

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