公开(公告)号：US20170062453A1

公开(公告)日：2017-03-02

申请号：US15348009

申请日：2016-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YUNGHWAN SON ,  JAESUNG SIM ,  SHINHWAN KANG ,  YOUNGWOO PARK ,  JAEDUK LEE

IPC: H01L27/115

CPC classification number: H01L27/11575 ,  G11C5/025 ,  G11C16/0483 ,  G11C16/30 ,  H01L27/11517 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/34

Abstract: A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.

Abstract translation: 一种三维（3D）半导体存储器件，其包括外围逻辑结构，该外围逻辑结构包括设置在半导体衬底上的外围逻辑电路和与外围逻辑电路重叠的第一绝缘层，以及在周边彼此间隔开的多个存储块 逻辑结构。 存储块中的至少一个包括阱板电极，与阱板电极的第一表面接触的半导体层，包括垂直堆叠在半导体层上的多个电极的堆叠结构，以及多个垂直结构穿透 堆叠结构并连接到半导体层。

公开(公告)号：US20170317096A1

公开(公告)日：2017-11-02

申请号：US15652411

申请日：2017-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOOCHEOL SHIN ,  HONGSOO KIM ,  JAESUNG SIM

IPC: H01L27/11556 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11548 ,  H01L27/11531 ,  H01L27/11582 ,  G11C16/04

CPC classification number: H01L27/11556 ,  G11C16/0483 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A three-dimensional semiconductor memory device includes stacked structures, vertical semiconductor patterns, common source regions, and well pickup regions. The stacked structures are disposed on a semiconductor layer of a first conductivity type. Each stacked structure includes electrodes vertically stacked on each other and is extended in a first direction. The vertical semiconductor patterns penetrate the stacked structures. The common source regions of a second conductivity type are disposed in the semiconductor layer. At least one common source region is disposed between two adjacent stacked structures. The at least one common source region is extended in the first direction. The well pickup regions of the first conductivity type are disposed in the semiconductor layer. At least one well pickup region is adjacent to both ends of at least one stacked structure.

公开(公告)号：US20180076212A1

公开(公告)日：2018-03-15

申请号：US15805513

申请日：2017-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YUNGHWAN SON ,  JAESUNG SIM ,  SHINHWAN KANG ,  YOUNGWOO PARK ,  JAEDUK LEE

IPC: H01L27/11575 ,  G11C5/02 ,  G11C16/04 ,  G11C16/30 ,  H01L27/1157 ,  H01L27/11517

CPC classification number: H01L27/11575 ,  G11C5/025 ,  G11C16/0483 ,  G11C16/30 ,  H01L27/11517 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/34

Abstract: A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.