公开(公告)号：US20170317096A1

公开(公告)日：2017-11-02

申请号：US15652411

申请日：2017-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOOCHEOL SHIN ,  HONGSOO KIM ,  JAESUNG SIM

IPC: H01L27/11556 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11548 ,  H01L27/11531 ,  H01L27/11582 ,  G11C16/04

CPC classification number: H01L27/11556 ,  G11C16/0483 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A three-dimensional semiconductor memory device includes stacked structures, vertical semiconductor patterns, common source regions, and well pickup regions. The stacked structures are disposed on a semiconductor layer of a first conductivity type. Each stacked structure includes electrodes vertically stacked on each other and is extended in a first direction. The vertical semiconductor patterns penetrate the stacked structures. The common source regions of a second conductivity type are disposed in the semiconductor layer. At least one common source region is disposed between two adjacent stacked structures. The at least one common source region is extended in the first direction. The well pickup regions of the first conductivity type are disposed in the semiconductor layer. At least one well pickup region is adjacent to both ends of at least one stacked structure.

公开(公告)号：US20210296324A1

公开(公告)日：2021-09-23

申请号：US17031037

申请日：2020-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONGHO LIM ,  HOOSUNG CHO ,  HONGSOO KIM

IPC: H01L27/115 ,  H01L23/522 ,  H01L21/768

Abstract: A vertical memory device includes circuit patterns of peripheral circuits on a substrate, the circuit patterns including a lower conductive pattern, cell stack structures over the circuit patterns and spaced apart in a first horizontal direction, wherein each of the cell stack structures includes gate electrodes spaced apart in a vertical direction, a first insulating interlayer covering the cell stack structures and a portion between the cell stack structures, a through via contact passing through the first insulating interlayer between the cell stack structures to contact an upper surface of the lower conductive pattern, at least one dummy through via contact passing through the first insulating interlayer between the cell stack structures and disposed adjacent to the through via contact, and upper wiring on the through via contact.

公开(公告)号：US20250149443A1

公开(公告)日：2025-05-08

申请号：US18533031

申请日：2023-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUJIN PARK ,  HONGSOO KIM ,  HEE-SUNG KAM ,  BYUNGJOO GO ,  Janghee JUNG

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device may include a source structure including a cell region and an extension region adjacent to the cell region, a gate stack in the cell and extension regions, a penetration contact disposed in the extension region, a stepwise insulating layer disposed on the gate, and an interconnection structure on the stepwise insulating layer. The interconnection structure may include a first interconnection insulating layer, a first lower conductive pattern in the first interconnection insulating layer, a capping layer on the first interconnection insulating layer, and a via structure penetrating the capping layer. The via structure may include a plurality of first vias connected to the first lower conductive pattern and connected to an upper conductive pattern, and the first vias may be disposed in the extension region.