公开(公告)号：US20230023911A1

公开(公告)日：2023-01-26

申请号：US17867962

申请日：2022-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEDUK LEE ,  JOONAM KIM ,  SEJUN PARK ,  RAEYOUNG LEE

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: Semiconductor devices are provided. The semiconductor devices may include a peripheral circuit structure, a memory cell block arranged on the peripheral circuit structure and including strings, each of which includes a lower select transistor, memory cell transistors, and an upper select transistor connected in series and stacked in a vertical direction, and bit lines on the memory cell block. The bit lines may include a first bit line electrically connected to first to third strings of the strings. The lower select transistors of the first to third strings include first to third lower select gate electrodes, respectively. The second lower select gate electrode may be arranged at a different vertical level from the first lower select gate electrode, and the third lower select gate electrode may be arranged at the same vertical level as the first lower select gate electrode.

公开(公告)号：US20200328227A1

公开(公告)日：2020-10-15

申请号：US16787195

申请日：2020-02-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIN-KYU KANG ,  WOOJAE JANG ,  CHANGSUB LEE ,  SEJUN PARK ,  JAEDUK LEE ,  JUNG HOON LEE

IPC: H01L27/11582 ,  H01L29/423 ,  H01L29/792

Abstract: A three-dimensional semiconductor memory device including a stack structure including gate structures and first dielectric patterns alternately stacked, a vertical channel penetrating the stack structure, and a charge storage layer extending from between the vertical channel and the first gate structures to between the vertical channel and the first dielectric patterns. The gate structures include first gate structures having a top surface and a bottom surface facing each other and having different width. The charge storage layer includes first segments between the vertical channel and the first gate structures, and second segments between the vertical channel and the first dielectric patterns. A thickness of the first segments is greater than a thickness of the second segments. One of the width of the top surface and the width of bottom surface of each first gate structure is the same as that of a first dielectric pattern on the first gate structure.

公开(公告)号：US20220139474A1

公开(公告)日：2022-05-05

申请号：US17384219

申请日：2021-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYEJI LEE ,  RAEYOUNG LEE ,  JINKYU KANG ,  SEJUN PARK ,  JAEDUK LEE

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

Abstract: A memory controller includes an over-program controller that preprograms and then erases the memory cells such that each of the memory cells has a first threshold voltage level, wherein fast cells are detected among the memory cells according to a threshold voltage less than or equal to a second threshold voltage less than the first threshold voltage, and a processor that generates fast cell information identifying the fast cells among the memory cells and stores the fast cell information in a buffer. The over-program controller controls the over-programming of the fast cells and normal programming of normal cells among the memory cells based on the fast cell information stored in the buffer.

公开(公告)号：US20160099155A1

公开(公告)日：2016-04-07

申请号：US14840114

申请日：2015-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEJUN PARK ,  DOHYUNG KIM ,  JAIHYUNG WON ,  SANGHO ROH ,  EUNSOL SHIN ,  SEUNG MOO LEE ,  GYUWAN CHOI

IPC: H01L21/308 ,  H01L29/66 ,  H01L21/762 ,  C23C16/50 ,  C23C16/26 ,  C23C14/06 ,  C23C16/30 ,  C23C14/22 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/3081 ,  C23C16/26 ,  C23C16/56 ,  H01L21/02115 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76224 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10888 ,  H01L29/4236

Abstract: A method of forming a hard mask layer on a substrate includes forming an amorphous carbon layer using nitrous oxide (N2O). A source of carbon and the nitrous oxide (N2O) are introduced to the substrate under a plasma ambient of an inert gas. The amorphous carbon layer has a nitrogen content ranging from about 0.05 at % to about 30 at % and an oxygen content ranging from about 0.05 at % to about 10 at %. In forming a semiconductor device, the hard mask layer is patterned, and a target layer beneath the hard mask layer is etched using the patterned hard mask layer as an etch mask.

Abstract translation: 在基板上形成硬掩模层的方法包括使用一氧化二氮（N2O）形成无定形碳层。 在惰性气体的等离子体环境下将碳源和一氧化二氮（N 2 O）源引入衬底。 无定形碳层的氮含量范围为约0.05at％至约30at％，氧含量为约0.05at％至约10at％。 在形成半导体器件时，硬掩模层被图案化，并且使用图案化的硬掩模层作为蚀刻掩模来蚀刻硬掩模层下面的目标层。