公开(公告)号：US20160027925A1

公开(公告)日：2016-01-28

申请号：US14875747

申请日：2015-10-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi SUNAMURA ,  Kishou KANEKO ,  Naoya FURUTAKE ,  Shinobu SAITOU ,  Yoshihiro HAYASHI

IPC: H01L29/786 ,  H01L27/092

CPC classification number: H01L27/1225 ,  H01L21/477 ,  H01L21/8254 ,  H01L27/0922 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/242 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/812

Abstract: A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view.

Abstract translation: 半导体器件具有p型金属氧化物半导体层; 与p型金属氧化物半导体层连接的源电极; 与p型金属氧化物半导体层连接的漏电极; 以及与p型金属氧化物半导体层的一部分相对配置的栅电极。 栅电极和漏电极在顶视图中彼此分离。

公开(公告)号：US20150200135A1

公开(公告)日：2015-07-16

申请号：US14667915

申请日：2015-03-25

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi SUNAMURA ,  Naoya INOUE ,  Kishou KANEKO

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L21/76895 ,  H01L21/76849 ,  H01L21/823885 ,  H01L23/49822 ,  H01L27/0688 ,  H01L27/10858 ,  H01L27/1104 ,  H01L27/11551 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/401 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and the second wire in the direction of stacking of the first wiring layer and the second wiring layer, and not coupled with the first wire and the second wire; a gate insulation film disposed over the side surface of the gate electrode; and a semiconductor layer disposed over the side surface of the gate electrode via the gate insulation film, and coupled with the first wire and the second wire.

Abstract translation: 提高了布置在多层布线层中的半导体元件的性能。 半导体器件包括：布置在第一布线层中的第一布线; 布置在层叠在第一布线层上的第二布线层中的第二布线; 栅电极，其在第一布线层和第二布线层的层叠方向上配置在第一布线和第二布线之间，不与第一布线和第二布线相连; 设置在所述栅电极的侧表面上的栅极绝缘膜; 以及通过栅极绝缘膜设置在栅电极的侧表面上并与第一线和第二线耦合的半导体层。

公开(公告)号：US20150171120A1

公开(公告)日：2015-06-18

申请号：US14633791

申请日：2015-02-27

Applicant: Renesas Electronics Corporation

Inventor： Kishou KANEKO ,  Naoya INOUE ,  Yoshihiro HAYASHI

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/49 ,  H01L21/465 ,  H01L21/4763 ,  H01L21/02 ,  H01L29/66 ,  H01L21/44

CPC classification number: H01L27/1259 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02565 ,  H01L21/28 ,  H01L21/44 ,  H01L21/465 ,  H01L21/47635 ,  H01L23/522 ,  H01L27/088 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1237 ,  H01L27/124 ,  H01L27/1251 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/66477 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interlayer insulating film is formed. Then a first gate electrode and a second gate electrode are buried in the interlayer insulating film. Then, an anti-diffusion film is formed over the interlayer insulating film, over the first gate electrode, and over the second gate electrode. Then, a first semiconductor layer is formed over the anti-diffusion film which is present over the first gate electrode. Then, an insulating cover film is formed over the upper surface and on the lateral side of the first semiconductor layer and over the anti-diffusion film. Then, a semiconductor film is formed over the insulating cover film. Then, the semiconductor film is removed selectively to leave a portion positioned over the second gate electrode, thereby forming a second semiconductor layer.

Abstract translation: 形成层间绝缘膜。 然后将第一栅电极和第二栅电极埋入层间绝缘膜中。 然后，在层间绝缘膜上方，在第一栅电极上方和第二栅电极上形成防扩散膜。 然后，在存在于第一栅电极上的抗扩散膜上形成第一半导体层。 然后，在第一半导体层的上表面和横向侧上以及反扩散膜之上形成绝缘覆盖膜。 然后，在绝缘覆盖膜上形成半导体膜。 然后，选择性地去除半导体膜以留下位于第二栅电极上的部分，从而形成第二半导体层。

公开(公告)号：US20130153888A1

公开(公告)日：2013-06-20

申请号：US13682297

申请日：2012-11-20

Applicant: Renesas Electronics Corporation

Inventor： Naoya INOUE ,  Kishou KANEKO ,  Yoshihiro HAYASHI

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76814 ,  H01L21/76879 ,  H01L23/522 ,  H01L23/53223 ,  H01L23/5329 ,  H01L28/60 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a semiconductor device provided with an active element in a multilayer interconnect layer and decreased in a chip area. A second interconnect layer is provided over a first interconnect layer. A first interlayer insulating layer is provided in the first interconnect layer. A semiconductor layer is provided in a second interconnect layer and in contact with the first interlayer insulating layer. A gate insulating film is provided over the semiconductor layer. A gate electrode is provided over the gate insulating film. At least two first vias are provided in the first interconnect layer and in contact by way of upper ends thereof with the semiconductor layer.

Abstract translation: 公开了一种半导体器件，其在多层互连层中设置有源元件并且在芯片面积上减小。 在第一互连层上提供第二互连层。 第一层间绝缘层设置在第一互连层中。 半导体层设置在第二互连层中并与第一层间绝缘层接触。 在半导体层上设置栅极绝缘膜。 在栅绝缘膜上设置栅电极。 至少两个第一通孔设置在第一互连层中并且通过其上端与半导体层接触。

公开(公告)号：US20160211173A1

公开(公告)日：2016-07-21

申请号：US15087427

申请日：2016-03-31

Applicant: Renesas Electronics Corporation

Inventor： Yoshihiro Hayashi ,  Naoya INOUE ,  Kishou KANEKO

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L21/76807 ,  H01L21/28282 ,  H01L21/76877 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/242 ,  H01L29/41 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/792

Abstract: The method of manufacturing a semiconductor device, including preparing a semiconductor substrate, forming a first insulating layer over said semiconductor substrate, forming first grooves in the first insulating film, forming a gate electrode and a first interconnect in the first grooves, respectively, forming a gate insulating film over the gate electrode, forming a semiconductor layer over the gate insulating, forming a second insulating layer over the semiconductor layer and the first insulating film, forming a via in the second insulating layer, and forming a second interconnect such that the second interconnect is connected to the semiconductor layer through the via. The gate electrode, the first interconnect and the second interconnect are formed by Cu or Cu alloy, respectively.

Abstract translation: 一种制造半导体器件的方法，包括制备半导体衬底，在所述半导体衬底上形成第一绝缘层，在第一绝缘膜中形成第一沟槽，分别在第一沟槽中形成栅电极和第一互连，形成 在所述栅电极上形成栅绝缘膜，在所述栅绝缘上形成半导体层，在所述半导体层和所述第一绝缘膜上形成第二绝缘层，在所述第二绝缘层中形成通孔，以及形成第二互连， 互连通过通孔连接到半导体层。 栅电极，第一互连和第二互连分别由Cu或Cu合金形成。

公开(公告)号：US20160172354A1

公开(公告)日：2016-06-16

申请号：US14995706

申请日：2016-01-14

Applicant: Renesas Electronics Corporation

Inventor： Kishou KANEKO ,  Naoya INOUE ,  Yoshihiro HAYASHI

IPC: H01L27/02 ,  H01L29/24 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/0285 ,  H01L23/522 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/552 ,  H01L27/0255 ,  H01L27/0296 ,  H01L27/0688 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate on which a semiconductor device is formed; first and second pads; a first insulating film which is formed above the semiconductor substrate; a plurality of wiring lines which are embedded in ditches provided in the first insulating film; a second insulating film provided to cover the first insulating film and the plurality of wiring lines; a semiconductor layer formed on the second insulating film; a source electrode connected with the semiconductor layer; and a drain electrode connected with the semiconductor layer. The plurality of wiring lines includes a gate electrode provided in a position which is opposite to the semiconductor layer. The semiconductor layer, the source electrode, the drain electrode and the gate electrode configure an ESD protection device to discharge a current by ESD surge from the first pad to the second pad.

Abstract translation: 半导体器件包括其上形成半导体器件的半导体衬底; 第一和第二垫; 形成在半导体衬底上的第一绝缘膜; 埋设在第一绝缘膜中的沟槽中的多条布线; 设置为覆盖所述第一绝缘膜和所述多条布线的第二绝缘膜; 形成在所述第二绝缘膜上的半导体层; 与半导体层连接的源电极; 以及与半导体层连接的漏电极。 多个布线包括设置在与半导体层相对的位置的栅电极。 半导体层，源电极，漏电极和栅电极构成ESD保护器件，以通过ESD浪涌从第一焊盘向第二焊盘放电。

公开(公告)号：US20150287832A1

公开(公告)日：2015-10-08

申请号：US14744261

申请日：2015-06-19

Applicant: Renesas Electronics Corporation

Inventor： Yoshihiro Hayashi ,  Naoya INOUE ,  Kishou KANEKO

IPC: H01L29/786 ,  H01L29/51 ,  H01L29/49 ,  H01L29/24 ,  H01L27/12 ,  H01L29/792

CPC classification number: H01L21/76807 ,  H01L21/28282 ,  H01L21/76877 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/242 ,  H01L29/41 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/792

Abstract: A semiconductor device including a semiconductor substrate, a first insulating layer formed over said semiconductor substrate, first grooves formed in said first insulating layer, a gate electrode and a first interconnect filled in said first grooves, respectively, a gate insulating film formed over said gate electrode, a semiconductor layer formed over said gate insulating, a second insulating layer formed over said semiconductor layer and said first insulating film, a via formed in said second insulating layer and connected to said semiconductor layer, a second groove formed in said second insulating layer, and a second interconnect filled in said second groove, formed over said via and connected to said via.

Abstract translation: 一种半导体器件，包括半导体衬底，形成在所述半导体衬底上的第一绝缘层，分别形成在所述第一绝缘层中的第一沟槽，栅电极和填充在所述第一沟槽中的第一互连，栅极绝缘膜分别形成在所述栅极 电极，形成在所述栅极绝缘上的半导体层，形成在所述半导体层和所述第一绝缘膜上的第二绝缘层，形成在所述第二绝缘层中并连接到所述半导体层的通孔，形成在所述第二绝缘层中的第二沟槽 以及填充在所述第二凹槽中的第二互连件，形成在所述通孔上并连接到所述通孔。

公开(公告)号：US20130200363A1

公开(公告)日：2013-08-08

申请号：US13738137

申请日：2013-01-10

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi SUNAMURA ,  Naoya INOUE ,  Kishou KANEKO

IPC: H01L27/105

CPC classification number: H01L29/7869 ,  H01L23/53228 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/101 ,  H01L27/105 ,  H01L27/1082 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/2436 ,  H01L29/22 ,  H01L29/24 ,  H01L29/7889 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a readily manufacturable semiconductor device including two transistors having mutually different characteristics. The semiconductor device includes a substrate, a multilayer wiring layer disposed over the substrate, a first transistor disposed in the multilayer wiring layer, and a second transistor disposed in a layer different from a layer including the first transistor disposed therein of the multilayer wiring layer, and having different characteristics from those of the first transistor. This can provide a readily manufacturable semiconductor device including two transistors having mutually different characteristics.

Abstract translation: 提供了包括具有相互不同特性的两个晶体管的容易制造的半导体器件。 半导体器件包括衬底，设置在衬底上的多层布线层，设置在多层布线层中的第一晶体管，以及设置在不同于布置在多层布线层中的第一晶体管的层的层中的第二晶体管， 并具有与第一晶体管不同的特性。 这可以提供包括具有相互不同特性的两个晶体管的容易制造的半导体器件。

公开(公告)号：US20130153887A1

公开(公告)日：2013-06-20

申请号：US13680757

申请日：2012-11-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kishou KANEKO ,  Naoya INOUE ,  Yoshihiro HAYASHI

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L27/1259 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02565 ,  H01L21/28 ,  H01L21/44 ,  H01L21/465 ,  H01L21/47635 ,  H01L23/522 ,  H01L27/088 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1237 ,  H01L27/124 ,  H01L27/1251 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/66477 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interlayer insulating film is formed. Then a first gate electrode and a second gate electrode are buried in the interlayer insulating film. Then, an anti-diffusion film is formed over the interlayer insulating film, over the first gate electrode, and over the second gate electrode. Then, a first semiconductor layer is formed over the anti-diffusion film which is present over the first gate electrode. Then, an insulating cover film is formed over the upper surface and on the lateral side of the first semiconductor layer and over the anti-diffusion film. Then, a semiconductor film is formed over the insulating cover film. Then, the semiconductor film is removed selectively to leave a portion positioned over the second gate electrode, thereby forming a second semiconductor layer.

Abstract translation: 形成层间绝缘膜。 然后将第一栅电极和第二栅电极埋入层间绝缘膜中。 然后，在层间绝缘膜上方，在第一栅电极上方和第二栅电极上形成防扩散膜。 然后，在存在于第一栅电极上的抗扩散膜上形成第一半导体层。 然后，在第一半导体层的上表面和横向侧上以及反扩散膜之上形成绝缘覆盖膜。 然后，在绝缘覆盖膜上形成半导体膜。 然后，选择性地去除半导体膜以留下位于第二栅电极上的部分，从而形成第二半导体层。

公开(公告)号：US20160240564A1

公开(公告)日：2016-08-18

申请号：US15139782

申请日：2016-04-27

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi SUNAMURA ,  Kishou KANEKO ,  Naoya FURUTAKE ,  Shinobu SAITOU ,  Yoshihiro HAYASHI

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/477 ,  H01L29/24 ,  H01L27/092

CPC classification number: H01L27/1225 ,  H01L21/477 ,  H01L21/8254 ,  H01L27/0922 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/242 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/812

Abstract: A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view.