Invention Application
- Patent Title: METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
- Patent Title (中): 制造半导体器件的方法
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Application No.: US14667915Application Date: 2015-03-25
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Publication No.: US20150200135A1Publication Date: 2015-07-16
- Inventor: Hiroshi SUNAMURA , Naoya INOUE , Kishou KANEKO
- Applicant: Renesas Electronics Corporation
- Priority: JP2012-021069 20120202
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L29/66

Abstract:
The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and the second wire in the direction of stacking of the first wiring layer and the second wiring layer, and not coupled with the first wire and the second wire; a gate insulation film disposed over the side surface of the gate electrode; and a semiconductor layer disposed over the side surface of the gate electrode via the gate insulation film, and coupled with the first wire and the second wire.
Public/Granted literature
- US09368403B2 Method for manufacturing a semiconductor device Public/Granted day:2016-06-14
Information query
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