公开(公告)号：US09633977B1

公开(公告)日：2017-04-25

申请号：US15040902

申请日：2016-02-10

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Shiqun Gu ,  Urmi Ray ,  Ratibor Radojcic

IPC: H01L25/065 ,  H05K1/14 ,  H01L23/538 ,  H01L23/498 ,  H01L25/16 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L25/0655 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/10 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/92144 ,  H01L2924/19105 ,  H05K1/14 ,  H05K1/148 ,  H05K1/185 ,  H05K3/4691 ,  H05K2201/09127 ,  H05K2201/10674 ,  H05K2203/0191

Abstract: Some features pertain to an integrated device that include a first integrated circuit (IC) package comprising a first laminated substrate, a flexible connector coupled to the first laminated substrate, and a second integrated circuit (IC) package comprising a second laminated substrate. The second laminated substrate is coupled to the flexible connector. The flexible connector includes a dielectric layer and an interconnect. The dielectric layer and the interconnect substantially extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer and the interconnect of the flexible connector, contiguously extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer extends into a substantial portion of the first laminated substrate. In some implementations, the dielectric layer includes polyimide (PI) layer.

公开(公告)号：US20170063079A1

公开(公告)日：2017-03-02

申请号：US14838034

申请日：2015-08-27

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Eugene Robert Worley ,  Ratibor Radojcic ,  Urmi Ray

IPC: H02H9/04

CPC classification number: H02H9/046 ,  H01L23/48 ,  H01L23/60 ,  H01L23/62 ,  H01L27/0255 ,  H01L27/0292 ,  H01L27/0296 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H02H9/044 ,  H01L2924/00012

Abstract: An integrated circuit (IC) package includes a die, a package substrate coupled to the die, and a first electrostatic discharge (ESD) protection component coupled to the package substrate, where the first electrostatic discharge (ESD) protection component is configured to provide package level electrostatic discharge (ESD) protection. In some implementations, the first electrostatic discharge (ESD) protection component is embedded in the package substrate. In some implementations, the die includes an internal electrostatic discharge (ESD) protection component configured to provide die level electrostatic discharge (ESD) protection. In some implementations, the internal electrostatic discharge (ESD) protection component and the first electrostatic discharge (ESD) protection component are configured to provide cumulative electrostatic discharge (ESD) protection for the die.

Abstract translation: 集成电路（IC）封装包括管芯，耦合到管芯的封装衬底以及耦合到封装衬底的第一静电放电（ESD）保护元件，其中第一静电放电（ESD）保护元件被配置为提供封装 级静电放电（ESD）保护。 在一些实施方案中，第一静电放电（ESD）保护组件嵌入在封装衬底中。 在一些实施方案中，管芯包括配置成提供管芯级静电放电（ESD）保护的内部静电放电（ESD）保护部件。 在一些实施方案中，内部静电放电（ESD）保护部件和第一静电放电（ESD）保护部件被配置为为管芯提供累积静电放电（ESD）保护。

公开(公告)号：US20140306349A1

公开(公告)日：2014-10-16

申请号：US13861086

申请日：2013-04-11

Applicant: QUALCOMM INCORPORATED

Inventor： Shiqun Gu ,  Urmi Ray ,  Roawen Chen ,  Brian Matthew Henderson ,  Ratibor Radojcic ,  Matthew Nowak ,  Nicholas Yu

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49811 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Some implementations provide an interposer that includes a substrate, a via in the substrate, and an oxidation layer. The via includes a metal material. The oxidation layer is between the via and the substrate. In some implementations, the substrate is a silicon substrate. In some implementations, the oxidation layer is a thermal oxide formed by exposing the substrate to heat. In some implementations, the oxidation layer is configured to provide electrical insulation between the via and the substrate. In some implementations, the interposer also includes an insulation layer. In some implementations, the insulation layer is a polymer layer. In some implementations, the interposer also includes at least one interconnect on the surface of the interposer. The at least one interconnect is positioned on the surface of the interposer such that the oxidation layer is between the interconnect and the substrate.

Abstract translation: 一些实施方案提供了一种插入器，其包括衬底，衬底中的通孔和氧化层。 通孔包括金属材料。 氧化层位于通孔和衬底之间。 在一些实施方式中，衬底是硅衬底。 在一些实施方案中，氧化层是通过将基底暴露于热而形成的热氧化物。 在一些实施方案中，氧化层被配置为在通孔和基底之间提供电绝缘。 在一些实施方案中，插入件还包括绝缘层。 在一些实施方案中，绝缘层是聚合物层。 在一些实现中，插入器还包括在插入器的表面上的至少一个互连。 所述至少一个互连件位于所述插入件的表面上，使得所述氧化层位于所述互连件和所述基板之间。

公开(公告)号：US09510454B2

公开(公告)日：2016-11-29

申请号：US14463367

申请日：2014-08-19

Applicant: QUALCOMM Incorporated

Inventor： Vidhya Ramachandran ,  Urmi Ray ,  Ravindra Vaman Shenoy ,  Kwan-Yu Lai ,  Jon Bradley Lasiter

IPC: H05K1/18 ,  H01L21/28 ,  H01L21/768 ,  H01L23/538 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L23/14 ,  H01L23/498 ,  H01L25/065

CPC classification number: H05K1/185 ,  H01L21/28008 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/84 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/5384 ,  H01L25/065 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/12 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

Abstract: An integrated interposer between a first component and a second component includes a substrate. The substrate may have thermal and/or mechanical properties with values lying between the thermal and/or mechanical properties of the first component and the second component. Active devices are disposed on a first surface of the substrate. A contact layer is coupled to the active devices and configured to couple at least the first component and a third component to the integrated interposer. At least one through via(s) is coupled to the contact layer and extends through the substrate to a second surface of the substrate. An interconnect layer is disposed on the second surface of the substrate and coupled to the at least one through via(s). The interconnect layer is configured to couple the second component to the integrated interposer.

Abstract translation: 第一部件和第二部件之间的集成插入件包括基板。 衬底可以具有热和/或机械性能，其中值位于第一部件和第二部件的热和/或机械性能之间。 有源器件设置在衬底的第一表面上。 接触层耦合到有源器件并且被配置为将至少第一部件和第三部件耦合到集成插入器。 至少一个通孔连接到接触层并且延伸穿过衬底到衬底的第二表面。 互连层设置在衬底的第二表面上并且耦合到至少一个通孔。 互连层被配置为将第二组件耦合到集成插入器。

公开(公告)号：US09209131B2

公开(公告)日：2015-12-08

申请号：US14160448

申请日：2014-01-21

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Ryan David Lane ,  Urmi Ray

IPC: H01L23/485 ,  H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L23/538

CPC classification number: H01L23/5227 ,  H01L21/76838 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/19 ,  H01L28/10 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some features pertain to an integrated device that includes a substrate, several metal layers coupled to the substrate, several dielectric layers coupled to the substrate, a first metal redistribution layer coupled to one of the metal layers, and a second metal redistribution layer coupled to the first metal redistribution layer. The first and second metal redistribution layers are configured to operate as a toroid inductor in the integrated device. In some implementations, the integrated device also includes a third metal redistribution layer. The third metal redistribution layer is coupled to the first and second metal redistribution layers. The third metal redistribution layer is a via. In some implementations, the first, second, and third metal redistribution layers are configured to operate as a toroid inductor in the integrated device. In some implementations, the first, second, and third redistribution layers form a set of windings for the toroid inductor.

Abstract translation: 一些特征涉及集成器件，其包括衬底，耦合到衬底的几个金属层，耦合到衬底的几个电介质层，耦合到金属层中的一个的第一金属再分布层，以及耦合到衬底的第二金属再分配层 第一金属再分配层。 第一和第二金属再分布层被配置为在集成器件中作为环形电感器工作。 在一些实施方案中，集成器件还包括第三金属再分配层。 第三金属再分布层耦合到第一和第二金属再分配层。 第三金属再分配层是通孔。 在一些实施方案中，第一，第二和第三金属再分配层被配置为在集成器件中作为环形电感器工作。 在一些实施方案中，第一，第二和第三再分配层形成用于环形电感器的一组绕组。

公开(公告)号：US09583460B2

公开(公告)日：2017-02-28

申请号：US14181371

申请日：2014-02-14

Applicant: QUALCOMM Incorporated

Inventor： Urmi Ray ,  Shiqun Gu

IPC: H01L25/065 ,  H01L23/48 ,  H01L21/48 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L21/568 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/73 ,  H01L24/81 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/24137 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92224 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/014

Abstract: Some features pertain to an integrated device that includes a dielectric layer configured as a base for the integrated device, several redistribution metal layers in the dielectric layer, a first wafer level die coupled to a first surface of the dielectric layer, and a second wafer level die coupled to the first wafer level die. The dielectric layer includes several dielectric layers. In some implementations, the first wafer level die is coupled to the redistribution metal layers through a first set of interconnects. In some implementations, the first wafer level die includes several through substrate vias (TSVs). In some implementations, the second wafer level die is coupled to the redistribution metal layers through a first set of interconnects, the TSVs, a second set of interconnects, and a set of solder balls. In some implementations, the integrated device includes an encapsulation layer that encapsulates the first and second wafer level dies.

Abstract translation: 一些特征涉及一种集成器件，其包括被配置为用于集成器件的基极的介质层，介电层中的几个再分布金属层，耦合到介电层的第一表面的第一晶片级管芯，以及第二晶片级 模具耦合到第一晶片级模具。 电介质层包括几个电介质层。 在一些实施方案中，第一晶片级管芯通过第一组互连件耦合到再分布金属层。 在一些实施方案中，第一晶片级管芯包括多个通过衬底通孔（TSV）。 在一些实施方案中，第二晶片级管芯通过第一组互连，TSV，第二组互连和一组焊球耦合到再分布金属层。 在一些实现中，集成器件包括封装第一和第二晶片级管芯的封装层。

公开(公告)号：US20150235988A1

公开(公告)日：2015-08-20

申请号：US14181371

申请日：2014-02-14

Applicant: QUALCOMM Incorporated

Inventor： Urmi Ray ,  Shiqun Gu

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L21/568 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/73 ,  H01L24/81 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/24137 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92224 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/014

Abstract: Some features pertain to an integrated device that includes a dielectric layer configured as a base for the integrated device, several redistribution metal layers in the dielectric layer, a first wafer level die coupled to a first surface of the dielectric layer, and a second wafer level die coupled to the first wafer level die. The dielectric layer includes several dielectric layers. In some implementations, the first wafer level die is coupled to the redistribution metal layers through a first set of interconnects. In some implementations, the first wafer level die includes several through substrate vias (TSVs). In some implementations, the second wafer level die is coupled to the redistribution metal layers through a first set of interconnects, the TSVs, a second set of interconnects, and a set of solder balls. In some implementations, the integrated device includes an encapsulation layer that encapsulates the first and second wafer level dies.

Abstract translation: 一些特征涉及一种集成器件，其包括被配置为用于集成器件的基极的介质层，介电层中的几个再分布金属层，耦合到介电层的第一表面的第一晶片级管芯，以及第二晶片级 模具耦合到第一晶片级模具。 电介质层包括几个电介质层。 在一些实施方案中，第一晶片级管芯通过第一组互连件耦合到再分布金属层。 在一些实施方案中，第一晶片级管芯包括多个通过衬底通孔（TSV）。 在一些实施方案中，第二晶片级管芯通过第一组互连，TSV，第二组互连和一组焊球耦合到再分布金属层。 在一些实现中，集成器件包括封装第一和第二晶片级管芯的封装层。

公开(公告)号：US20140264836A1

公开(公告)日：2014-09-18

申请号：US13839816

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter Tamio Chun ,  Jungwon Suh ,  Urmi Ray ,  Shiqun Gu

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L23/16 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/3737 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/13 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/11

Abstract: An integrated circuit package is disclosed that includes a first-pitch die and a second-pitch die. The second-pitch die interconnects to the second-pitch substrate through second-pitch substrates. The first-pitch die interconnects through first-pitch interconnects to an interposer adapter. The pitch of the first-pitch interconnects is too fine for the second-pitch substrate. But the interposer adapter interconnects through second-pitch interconnects to the second-pitch substrate and includes through substrate vias so that I/O signaling between the first-pitch die and the second-pitch die can be conducted through the second-pitch substrate and through the through substrate vias in the interposer adapter.

Abstract translation: 公开了一种集成电路封装，其包括第一间距管芯和第二间距管芯。 第二间距模具通过第二间距基板与第二间距基板相互连接。 第一间距模具通过第一间距互连件互连到插入器适配器。 第一节距互连的间距对于第二间距衬底来说太细了。 但是插入器适配器通过第二间距互连件连接到第二间距衬底并且包括通过衬底通孔，使得第一间距管芯和第二间距管芯之间的I / O信号可以通过第二间距衬底并且通过 贯穿衬底通孔插入插座适配器中。

公开(公告)号：US20160049340A1

公开(公告)日：2016-02-18

申请号：US14460805

申请日：2014-08-15

Applicant: QUALCOMM INCORPORATED

Inventor： Vidhya Ramachandran ,  Urmi Ray

IPC: H01L21/66 ,  H01L23/48 ,  G01B7/16 ,  H01L23/00

CPC classification number: H01L22/14 ,  G01B7/16 ,  G01B2210/56 ,  H01L22/34 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/562 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/023 ,  H01L2224/16227 ,  H01L2224/73257 ,  H01L2224/81191 ,  H01L2224/81908 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/0549 ,  H01L2924/14 ,  H01L2924/19107 ,  H01L2924/35 ,  H01L2924/3511 ,  H01L2924/384

Abstract: In a particular embodiment, an apparatus includes a stress sensor located on a first side of a semiconductor device. The apparatus further includes circuitry located on a second side of the semiconductor device. The stress sensor is configured to detect stress at the semiconductor device. In another particular embodiment, a method includes receiving data from a stress sensor located on a first side of a packaged semiconductor device. The packaged semiconductor device includes circuitry located on a second side of the packaged semiconductor device. The data indicates stress detected by the stress sensor. The method further includes performing a test associated with the packaged semiconductor device based on the data.

Abstract translation: 在特定实施例中，一种装置包括位于半导体器件的第一侧上的应力传感器。 该装置还包括位于半导体器件的第二侧上的电路。 应力传感器被配置为检测半导体器件处的应力。 在另一个具体实施例中，一种方法包括从位于封装半导体器件的第一侧上的应力传感器接收数据。 封装的半导体器件包括位于封装的半导体器件的第二侧上的电路。 数据表示应力传感器检测到的应力。 该方法还包括基于该数据执行与封装半导体器件相关联的测试。

公开(公告)号：US20150206837A1

公开(公告)日：2015-07-23

申请号：US14160448

申请日：2014-01-21

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Ryan David Lane ,  Urmi Ray

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5227 ,  H01L21/76838 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/19 ,  H01L28/10 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some features pertain to an integrated device that includes a substrate, several metal layers coupled to the substrate, several dielectric layers coupled to the substrate, a first metal redistribution layer coupled to one of the metal layers, and a second metal redistribution layer coupled to the first metal redistribution layer. The first and second metal redistribution layers are configured to operate as a toroid inductor in the integrated device. In some implementations, the integrated device also includes a third metal redistribution layer. The third metal redistribution layer is coupled to the first and second metal redistribution layers. The third metal redistribution layer is a via. In some implementations, the first, second, and third metal redistribution layers are configured to operate as a toroid inductor in the integrated device. In some implementations, the first, second, and third redistribution layers form a set of windings for the toroid inductor.

Abstract translation: 一些特征涉及集成器件，其包括衬底，耦合到衬底的几个金属层，耦合到衬底的几个电介质层，耦合到金属层中的一个的第一金属再分布层，以及耦合到衬底的第二金属再分配层 第一金属再分配层。 第一和第二金属再分布层被配置为在集成器件中作为环形电感器工作。 在一些实施方案中，集成器件还包括第三金属再分配层。 第三金属再分布层耦合到第一和第二金属再分配层。 第三金属再分配层是通孔。 在一些实施方案中，第一，第二和第三金属再分配层被配置为在集成器件中作为环形电感器工作。 在一些实施方案中，第一，第二和第三再分配层形成用于环形电感器的一组绕组。