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公开(公告)号：US09990024B2
公开(公告)日：2018-06-05
申请号：US14849343
申请日：2015-09-09
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/3206 , G06F1/324 , Y02D10/126 , Y02D10/172
摘要： A method including receiving an indication of a number of active processing units in a computer processor; in response to receiving the indication, determining an appropriate operating voltage margin for the computer processor; reducing an operating frequency of the active processing units in response to receiving the indication; adjusting a power supply to increase or decrease a voltage to the computer processor in accordance with the appropriate operating voltage margin; and increasing the operating frequency of the active processing units in response to an acknowledgment that the power supply has been adjusted.
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公开(公告)号：US20170364140A1
公开(公告)日：2017-12-21
申请号：US15187426
申请日：2016-06-20
发明人： Sarbartha Banerjee , Pawan Chhabra , Navid Toosizadeh , Sreekanth Nallagatla , Shih-Hsin Jason Hu
CPC分类号： G06F1/3296 , G06F1/08 , G06F1/3206 , G06F1/3228 , G06F1/324
摘要： A hardware system is disclosed for active-core-based performance boost. In an example aspect, the hardware system includes multiple cores and a power mode manager. Each core can be powered up if active or powered down if inactive. The power mode manager manages a power mode collection including an independent power mode collection and an active-core-dependent power mode collection. The power mode manager includes a software-accessible power mode manager and a hardware-reserved power mode manager. The software-accessible power mode manager provides a power-mode-triggering pathway to enable software to trigger activation of an independent power mode of the independent power mode collection. The hardware-reserved power mode manager excludes the software from being able to trigger activation of a dependent power mode of the active-core-dependent power mode collection and triggers activation of a dependent power mode of the active-core-dependent collection based on a number of active cores of the multiple cores.
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公开(公告)号：US09858217B1
公开(公告)日：2018-01-02
申请号：US15197524
申请日：2016-06-29
CPC分类号： G06F13/1689 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F1/3296 , G11C5/14 , G11C7/04 , G11C7/1072 , G11C7/22 , G11C7/227 , G11C11/417
摘要： An apparatus includes a memory, a timing circuit configured to emulate a first operation of the memory to activate a second operation of the memory, a sensor configured to emulate a portion of the timing circuit, and a controller configured to adjust an operating parameter of the memory based on the sensor emulating the portion of the timing circuit. A method is presented. The method includes at least operating a timing circuit to emulate a first operation of the memory, activating a second operation of the memory based on the emulating the first operation of the memory, emulating, by a sensor, a portion of the timing circuit. Another apparatus is presented. The apparatus includes at least a memory, a timing circuit, and means for tracking a performance of the memory based on the timing circuit tracking a memory operation.
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公开(公告)号：US09651969B2
公开(公告)日：2017-05-16
申请号：US14814112
申请日：2015-07-30
CPC分类号： G05F1/625 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method of setting a supply voltage in a device is disclosed. The method includes receiving a first plurality of inputs from a plurality of sensors that are representative of a gate delay of a signal path on the device, and receiving a second plurality of inputs from a plurality of temperature sensors. The method further includes estimating a plurality of interconnect delays for the signal path based on the second plurality of inputs, and determining the supply voltage for the signal path based on the first plurality of inputs and the plurality of interconnect delays.
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5.发明申请公开(公告)号：US20160003893A1
公开(公告)日：2016-01-07
申请号：US14323652
申请日：2014-07-03
IPC分类号： G01R31/28
CPC分类号： G01R31/2851 , G06F1/26 , G06F1/3203 , G06F1/3206 , G06F1/3287 , G06F1/3296 , Y02D10/171 , Y02D10/172
摘要： The systems and method described herein provide efficient (e.g., low power and low area) means to track performance in numerous supply domains with heterogeneous circuits that are used in a large system-on-a-chip integrated circuit (SoCs). The heterogeneous circuits can include circuits made with different devices, different cell libraries, and different hard macros that are in different power supply domains. Performance measurements from performance sensors (or process-voltage-temperature (PVT) sensors) that are spread about the SoC are collected and processed to determine voltage levels for each of the supply domains. A single controller can receive can determine voltage levels for a whole SoC. The performance sensors are connected to the controller by a scan chain. The technique is flexible and can be easily adapted for use in SoCs with different power supply domains and types of circuits.
摘要翻译： 本文描述的系统和方法提供了有效（例如，低功率和低面积）的方式来跟踪在大型片上系统集成电路（SoC）中使用的异质电路的多个供电域中的性能。 异构电路可以包括由不同设备制成的电路，不同的单元库以及不同电源域中的不同硬宏。 收集和处理围绕SoC传播的性能传感器（或过程电压 - 温度（PVT）传感器）的性能测量，以确定每个供应域的电压电平。 单个控制器可以接收可以确定整个SoC的电压电平。 性能传感器通过扫描链连接到控制器。 该技术是灵活的，可以轻松地适用于具有不同电源域和电路类型的SoC。
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公开(公告)号：US11249530B1
公开(公告)日：2022-02-15
申请号：US17105253
申请日：2020-11-25
摘要： In certain aspects, a system includes a voltage controller, wherein the voltage controller includes switches coupled between a voltage supply rail and an output of the voltage controller, each of the switches having a control input, and a control circuit coupled to the control inputs of the switches. The system also includes a timing circuit coupled to the control circuit, wherein the timing circuit includes a delay line, and flops, each of the flops having an input and an output, wherein the input of each of the flops is coupled to a respective node on the delay line, and the outputs of the flops are coupled to the control circuit.
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公开(公告)号：US20180183417A1
公开(公告)日：2018-06-28
申请号：US15393107
申请日：2016-12-28
发明人： Lam Ho , Keith Alan Bowman , Navid Toosizadeh , Shih-Hsin Jason Hu , Mohammad Reza Kakoee , Saravana Krishnan Kannan
CPC分类号： H03K5/05 , G06F1/10 , G06F1/305 , H03K5/19 , H03K2005/00019
摘要： In certain aspects, a system comprises a voltage-droop mitigation circuit configured to monitor voltage droop in a supply voltage supplied to a circuit, and to perform voltage-droop mitigation for the circuit if the monitored voltage droop is equal to or greater than a droop threshold. In one aspect, the system also includes a performance monitor configured to track a number of clock cycles over which the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of clock cycles. In another aspect, the system also includes a performance monitor configured to track a number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within the time duration.
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8.发明申请公开(公告)号：US20170031376A1
公开(公告)日：2017-02-02
申请号：US14814112
申请日：2015-07-30
IPC分类号： G05F1/625
CPC分类号： G05F1/625 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method of setting a supply voltage in a device is disclosed. The method includes receiving a first plurality of inputs from a plurality of sensors that are representative of a gate delay of a signal path on the device, and receiving a second plurality of inputs from a plurality of temperature sensors. The method further includes estimating a plurality of interconnect delays for the signal path based on the second plurality of inputs, and determining the supply voltage for the signal path based on the first plurality of inputs and the plurality of interconnect delays.
摘要翻译： 公开了一种在设备中设置电源电压的方法。 该方法包括从代表设备上的信号路径的门延迟的多个传感器接收第一多个输入，以及从多个温度传感器接收第二多个输入。 该方法还包括基于第二多个输入来估计用于信号路径的多个互连延迟，以及基于第一多个输入和多个互连延迟确定用于信号路径的电源电压。
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公开(公告)号：US09733694B2
公开(公告)日：2017-08-15
申请号：US14839836
申请日：2015-08-28
发明人： Hee Jun Park , Krishna V. S. S. S. R. Vanka , Sravan Kumar Ambapuram , Shirish Kumar Agarwal , Shih-Hsin Jason Hu
CPC分类号： G06F1/3296 , G06F1/3206 , G06F1/3234 , G06F1/324 , G06F1/329 , H04W52/0251 , Y02D10/126 , Y02D10/172 , Y02D70/1262 , Y02D70/142 , Y02D70/144 , Y02D70/164
摘要： Systems and methods for dynamically adjusting an input parameter, such as power supply level, to a shared power domain in a portable computing device are disclosed. The power domain includes a plurality of processing resources that share the power source. The power supply level is reduced based on a critical core vote pool derived from votes from the plurality of processing resources. The critical core vote pool is narrowed from all the votes by disqualifying votes based on the operating status of the associated processing resources. For example, because inactive processing resources may be unaffected by a change in the voltage level to the shared domain, and because certain active processing resources are in a position to adjust to a power change dictated by another processing resource, such processing resources may be considered noncritical and their votes disqualified from consideration.
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公开(公告)号：US09612636B2
公开(公告)日：2017-04-04
申请号：US14497258
申请日：2014-09-25
发明人： Matthew Levi Severson , Shih-Hsin Jason Hu , Dipti Ranjan Pal , Madan Krishnappa , Jeffrey Gemar , Noman Ahmed , Mohammad Tamjidi , Mark Kempfert
CPC分类号： G06F1/26 , G06F1/32 , G06F1/3287 , G06F9/4405 , Y02D10/171
摘要： A method for operating an electronic apparatus is provided. The method includes receiving a token, activating a power switch for powering up a core in response to the receiving the token, and outputting the token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. In one aspect, an electronic apparatus includes a power switch configured to power up to a core is provided. A power-switch control circuit is configured to receive a token, activate the power switch for powering up the core in response to receiving the token, output the received token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. A plurality of the power-switch control circuits is configured as a ring.
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