公开(公告)号：US10409317B2

公开(公告)日：2019-09-10

申请号：US15614358

申请日：2017-06-05

Applicant: QUALCOMM Incorporated

Inventor： Martin Saint-Laurent ,  Lam Ho ,  Carlos Andres Rodriguez Ancer ,  Bhavin Shah

IPC: G06F17/50 ,  G06F1/03 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/10 ,  H03K21/40 ,  G06F1/08 ,  H03K19/00 ,  H03K3/012 ,  H03K5/131

Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

公开(公告)号：US20180284859A1

公开(公告)日：2018-10-04

申请号：US15471692

申请日：2017-03-28

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Rajeev Jain ,  Sassan Shahrokhinia ,  Lam Ho

IPC: G06F1/26

CPC classification number: G06F1/263 ,  H02J1/08 ,  H02J1/108

Abstract: An integrated circuit is disclosed for power multiplexing with an active load. In an example aspect, the integrated circuit includes a first power rail, a second power rail, a load power rail, multiple power-multiplexer tiles, and power-multiplexer control circuitry. The first power rail is at a first voltage, and the second power rail is at a second voltage. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and jointly perform a power-multiplexing operation responsive to a power-rail switching signal. Each power-multiplexer tile switches between coupling the load power rail to the first power rail and the second power rail. The power-multiplexer control circuitry is coupled to the first and second power rails and includes a comparator to produce a relative voltage signal based on the first and second voltages. The power-multiplexer control circuitry generates the power-rail switching signal based on the relative voltage signal.

公开(公告)号：US10009016B1

公开(公告)日：2018-06-26

申请号：US15393107

申请日：2016-12-28

Applicant: QUALCOMM Incorporated

Inventor： Lam Ho ,  Keith Alan Bowman ,  Navid Toosizadeh ,  Shih-Hsin Jason Hu ,  Mohammad Reza Kakoee ,  Saravana Krishnan Kannan

IPC: G01R31/00 ,  G01R19/00 ,  H03K5/05 ,  H03K5/19 ,  H03K5/00

Abstract: In certain aspects, a system comprises a voltage-droop mitigation circuit configured to monitor voltage droop in a supply voltage supplied to a circuit, and to perform voltage-droop mitigation for the circuit if the monitored voltage droop is equal to or greater than a droop threshold. In one aspect, the system also includes a performance monitor configured to track a number of clock cycles over which the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of clock cycles. In another aspect, the system also includes a performance monitor configured to track a number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within the time duration.

公开(公告)号：US20180348809A1

公开(公告)日：2018-12-06

申请号：US15614358

申请日：2017-06-05

Applicant: QUALCOMM Incorporated

Inventor： Martin Saint-Laurent ,  Lam Ho ,  Carlos Andres Rodriguez Ancer ,  Bhavin Shah

IPC: G06F1/03 ,  G06F1/32 ,  G06F1/10 ,  H03K21/40

CPC classification number: G06F1/0321 ,  G06F1/08 ,  G06F1/10 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/324 ,  H03K3/012 ,  H03K5/131 ,  H03K19/0016 ,  H03K21/406

Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

公开(公告)号：US20180183417A1

公开(公告)日：2018-06-28

申请号：US15393107

申请日：2016-12-28

Applicant: QUALCOMM Incorporated

Inventor： Lam Ho ,  Keith Alan Bowman ,  Navid Toosizadeh ,  Shih-Hsin Jason Hu ,  Mohammad Reza Kakoee ,  Saravana Krishnan Kannan

IPC: H03K5/05 ,  H03K5/19

CPC classification number: H03K5/05 ,  G06F1/10 ,  G06F1/305 ,  H03K5/19 ,  H03K2005/00019

Abstract: In certain aspects, a system comprises a voltage-droop mitigation circuit configured to monitor voltage droop in a supply voltage supplied to a circuit, and to perform voltage-droop mitigation for the circuit if the monitored voltage droop is equal to or greater than a droop threshold. In one aspect, the system also includes a performance monitor configured to track a number of clock cycles over which the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of clock cycles. In another aspect, the system also includes a performance monitor configured to track a number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within the time duration.

公开(公告)号：US11347256B2

公开(公告)日：2022-05-31

申请号：US17143124

申请日：2021-01-06

Applicant: QUALCOMM Incorporated

Inventor： Martin Saint-Laurent ,  Lam Ho ,  Carlos Andres Rodriguez Ancer ,  Bhavin Shah

IPC: G06F1/03 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/10 ,  H03K21/40 ,  G06F1/08 ,  H03K19/00 ,  H03K3/012 ,  H03K5/131

Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

公开(公告)号：US10890937B2

公开(公告)日：2021-01-12

申请号：US16193410

申请日：2018-11-16

Applicant: QUALCOMM Incorporated

Inventor： Martin Saint-Laurent ,  Lam Ho ,  Carlos Andres Rodriguez Ancer ,  Bhavin Shah

IPC: G06F1/03 ,  G06F1/08 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/10 ,  H03K3/012 ,  H03K19/00 ,  H03K5/131 ,  H03K21/40

Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

公开(公告)号：US10317968B2

公开(公告)日：2019-06-11

申请号：US15471692

申请日：2017-03-28

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Rajeev Jain ,  Sassan Shahrokhinia ,  Lam Ho

IPC: G06F1/26 ,  H02J1/08 ,  H02J1/10

Abstract: An integrated circuit is disclosed for power multiplexing with an active load. In an example aspect, the integrated circuit includes a first power rail, a second power rail, a load power rail, multiple power-multiplexer tiles, and power-multiplexer control circuitry. The first power rail is at a first voltage, and the second power rail is at a second voltage. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and jointly perform a power-multiplexing operation responsive to a power-rail switching signal. Each power-multiplexer tile switches between coupling the load power rail to the first power rail and the second power rail. The power-multiplexer control circuitry is coupled to the first and second power rails and includes a comparator to produce a relative voltage signal based on the first and second voltages. The power-multiplexer control circuitry generates the power-rail switching signal based on the relative voltage signal.