公开(公告)号：US20180183417A1

公开(公告)日：2018-06-28

申请号：US15393107

申请日：2016-12-28

Applicant: QUALCOMM Incorporated

Inventor： Lam Ho ,  Keith Alan Bowman ,  Navid Toosizadeh ,  Shih-Hsin Jason Hu ,  Mohammad Reza Kakoee ,  Saravana Krishnan Kannan

IPC: H03K5/05 ,  H03K5/19

CPC classification number: H03K5/05 ,  G06F1/10 ,  G06F1/305 ,  H03K5/19 ,  H03K2005/00019

Abstract: In certain aspects, a system comprises a voltage-droop mitigation circuit configured to monitor voltage droop in a supply voltage supplied to a circuit, and to perform voltage-droop mitigation for the circuit if the monitored voltage droop is equal to or greater than a droop threshold. In one aspect, the system also includes a performance monitor configured to track a number of clock cycles over which the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of clock cycles. In another aspect, the system also includes a performance monitor configured to track a number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within the time duration.

公开(公告)号：US09990024B2

公开(公告)日：2018-06-05

申请号：US14849343

申请日：2015-09-09

Applicant: QUALCOMM Incorporated

Inventor： Navid Toosizadeh ,  Mohammad Reza Kakoee ,  Shih-Hsin Jason Hu ,  Mohamed Waleed Allam

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172

Abstract: A method including receiving an indication of a number of active processing units in a computer processor; in response to receiving the indication, determining an appropriate operating voltage margin for the computer processor; reducing an operating frequency of the active processing units in response to receiving the indication; adjusting a power supply to increase or decrease a voltage to the computer processor in accordance with the appropriate operating voltage margin; and increasing the operating frequency of the active processing units in response to an acknowledgment that the power supply has been adjusted.

公开(公告)号：US20170364140A1

公开(公告)日：2017-12-21

申请号：US15187426

申请日：2016-06-20

Applicant: QUALCOMM Incorporated

Inventor： Sarbartha Banerjee ,  Pawan Chhabra ,  Navid Toosizadeh ,  Sreekanth Nallagatla ,  Shih-Hsin Jason Hu

IPC: G06F1/32 ,  G06F1/08

CPC classification number: G06F1/3296 ,  G06F1/08 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324

Abstract: A hardware system is disclosed for active-core-based performance boost. In an example aspect, the hardware system includes multiple cores and a power mode manager. Each core can be powered up if active or powered down if inactive. The power mode manager manages a power mode collection including an independent power mode collection and an active-core-dependent power mode collection. The power mode manager includes a software-accessible power mode manager and a hardware-reserved power mode manager. The software-accessible power mode manager provides a power-mode-triggering pathway to enable software to trigger activation of an independent power mode of the independent power mode collection. The hardware-reserved power mode manager excludes the software from being able to trigger activation of a dependent power mode of the active-core-dependent power mode collection and triggers activation of a dependent power mode of the active-core-dependent collection based on a number of active cores of the multiple cores.

公开(公告)号：US09484892B1

公开(公告)日：2016-11-01

申请号：US14850801

申请日：2015-09-10

Applicant: QUALCOMM Incorporated

Inventor： Mohammad Reza Kakoee ,  Shih-Hsin Jason Hu ,  Min Chen ,  Jasmin Smaila Ibrahimovic ,  Carlos Auyon ,  Sorin Adrian Dobre ,  Navid Toosizadeh ,  Nan Chen ,  Mohamed Waleed Allam

IPC: G01R31/317 ,  H03K3/011 ,  H03K3/012

CPC classification number: H03K3/011 ,  G01R31/2884 ,  G01R31/31727 ,  H03K3/012

Abstract: An integrated circuit compensates for circuit aging by measuring the aging with an aging sensor and controlling a supply voltage based on the measured aging. The operating environment for the aging sensor can be set to reduce impacts of non-aging effects on the measured aging. For example, the operating environment can use a temperature inversion voltage. An initial aging measurement value which is the difference between an initial aged measurement and an initial unaged measurement can be stored on the integrated circuit. A core power reduction controller can use the measured aging and the stored initial aging measurement value to update a performance-sensor target value and then perform adaptive voltage scaling using the using the updated performance-sensor target value.

Abstract translation: 集成电路通过使用老化传感器测量老化并根据测量的老化来控制电源电压来补偿电路老化。 老化传感器的操作环境可以设置为减少非老化对测量老化的影响。 例如，操作环境可以使用温度反转电压。 初始老化测量值与初始未老化测量值之差可以存储在集成电路上。 核心功率降低控制器可以使用测量的老化和存储的初始老化测量值来更新性能传感器目标值，然后使用更新的性能传感器目标值来执行自适应电压缩放。

公开(公告)号：US10587253B1

公开(公告)日：2020-03-10

申请号：US16205093

申请日：2018-11-29

Applicant: QUALCOMM Incorporated

Inventor： Yu Huang ,  Nam Dang ,  Keith Alan Bowman ,  Navid Toosizadeh

IPC: G06F1/04 ,  H03K5/1534 ,  H03K5/135 ,  H03K3/03 ,  H03K21/38 ,  H03K19/20 ,  H03K5/00

Abstract: A programmable delay line includes a pulse generator configured to generate a pulse in response to a transition of an input signal; an oscillator configured to generate a clock in response to the pulse; a counter configured to change a current count from a first value towards a second value in response to periods of the clock; and a gating device configured to output the transition of the input signal to generate an output signal in response to the current count reaching the second value. The delay of the input signal is a function of the difference between the first value and the second value. The delay line may be used in different applications, such as a dynamic variation monitor (DVM) configured to detect supply voltage droop. The DVM may be in an adaptive clock distribution (ACD) to reduce the clock frequency for a datapath in response to a droop.

公开(公告)号：US10359833B2

公开(公告)日：2019-07-23

申请号：US15187426

申请日：2016-06-20

Applicant: QUALCOMM Incorporated

Inventor： Sarbartha Banerjee ,  Pawan Chhabra ,  Navid Toosizadeh ,  Sreekanth Nallagatla ,  Shih-Hsin Jason Hu

IPC: G06F1/3206 ,  G06F1/3296 ,  G06F1/08 ,  G06F1/3228 ,  G06F1/324

Abstract: A hardware system is disclosed for active-core-based performance boost. In an example aspect, the hardware system includes multiple cores and a power mode manager. Each core can be powered up if active or powered down if inactive. The power mode manager manages a power mode collection including an independent power mode collection and an active-core-dependent power mode collection. The power mode manager includes a software-accessible power mode manager and a hardware-reserved power mode manager. The software-accessible power mode manager provides a power-mode-triggering pathway to enable software to trigger activation of an independent power mode of the independent power mode collection. The hardware-reserved power mode manager excludes the software from being able to trigger activation of a dependent power mode of the active-core-dependent power mode collection and triggers activation of a dependent power mode of the active-core-dependent collection based on a number of active cores of the multiple cores.

公开(公告)号：US10009016B1

公开(公告)日：2018-06-26

申请号：US15393107

申请日：2016-12-28

Applicant: QUALCOMM Incorporated

Inventor： Lam Ho ,  Keith Alan Bowman ,  Navid Toosizadeh ,  Shih-Hsin Jason Hu ,  Mohammad Reza Kakoee ,  Saravana Krishnan Kannan

IPC: G01R31/00 ,  G01R19/00 ,  H03K5/05 ,  H03K5/19 ,  H03K5/00

Abstract: In certain aspects, a system comprises a voltage-droop mitigation circuit configured to monitor voltage droop in a supply voltage supplied to a circuit, and to perform voltage-droop mitigation for the circuit if the monitored voltage droop is equal to or greater than a droop threshold. In one aspect, the system also includes a performance monitor configured to track a number of clock cycles over which the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of clock cycles. In another aspect, the system also includes a performance monitor configured to track a number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within the time duration.

公开(公告)号：US20170068309A1

公开(公告)日：2017-03-09

申请号：US14849343

申请日：2015-09-09

Applicant: QUALCOMM Incorporated

Inventor： Navid Toosizadeh ,  Mohammad Reza Kakoee ,  Shih-Hsin Jason Hu ,  Mohamed Waleed Allam

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172

Abstract: A method including receiving an indication of a number of active processing units in a computer processor; in response to receiving the indication, determining an appropriate operating voltage margin for the computer processor; reducing an operating frequency of the active processing units in response to receiving the indication; adjusting a power supply to increase or decrease a voltage to the computer processor in accordance with the appropriate operating voltage margin; and increasing the operating frequency of the active processing units in response to an acknowledgment that the power supply has been adjusted.

Abstract translation: 一种方法，包括在计算机处理器中接收多个活动处理单元的指示; 响应于接收到所述指示，确定所述计算机处理器的适当的工作电压裕度; 响应于接收到所述指示而减少所述活动处理单元的操作频率; 调整电源以根据适当的工作电压余量增加或减少计算机处理器的电压; 以及响应于已经调整了电源的确认来增加主动处理单元的操作频率。