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    Bit writability implementation for memories
    3.
    发明授权
    Bit writability implementation for memories 有权

    公开(公告)号：US09875776B1

    公开(公告)日：2018-01-23

    申请号：US15363401

    申请日：2016-11-29

    Applicant: QUALCOMM Incorporated

    Inventor： Priyankar Mathuria ,  Rakesh Kumar Sinha ,  Sharad Kumar Gupta

    IPC: G11C7/00 ,  G11C7/12 ,  G11C7/10

    CPC classification number: G11C7/1009 ,  G11C7/1084 ,  G11C2207/2227

    Abstract: Maskable level shifter circuits and memories are provided. Memories may include a plurality of memory cells and a bitline coupled to the plurality of memory cells. The memories includes a maskable level shifter configured to receive write data and a mask signal. A maskable level shifter includes a level shifter configured to level shift the write data and output the level shifted write data to the bitline when the mask signal is inactive and a masking circuit configured to remove power from the level shifter when the mask signal is active. Another maskable level shifter includes a level shifter configured to level shift the write data and output the level shifted write data to the bitline when the mask signal is inactive and a masking circuit configured to output a predetermined state to the bitline when the mask signal is active.

    Memory with multiple word line design
    7.
    发明授权
    Memory with multiple word line design 有权
    具有多个字线设计的内存

    公开(公告)号：US08929153B1

    公开(公告)日：2015-01-06

    申请号：US13975254

    申请日：2013-08-23

    Applicant: QUALCOMM Incorporated

    Inventor： Chirag Gulati ,  Rakesh Kumar Sinha ,  Ritu Chaba ,  Sei Seung Yoon

    IPC: G11C7/00 ,  G11C11/419

    CPC classification number: G11C11/419 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418

    Abstract: Disclosed are various apparatuses and methods for a memory with a multiple read word line design. A memory may include a plurality of bit cells arranged in a row, a first read word line connected to a first subset of the plurality of bit cells, and a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells. A method may include asserting, during a first read operation, a first read word line connected to a first subset of a plurality of bit cells arranged in a row of bit cells, and asserting, during a second read operation, a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells.

    Abstract translation: 公开了具有多重读取字线设计的存储器的各种装置和方法。 存储器可以包括排列成行的多个比特单元，连接到多个比特单元的第一子集的第一读取字线和连接到多个比特单元的第二子集的第二读取字线，其中 第一和第二子集位于同一行位单元格中。 一种方法可以包括在第一读取操作期间断言连接到排列在位单元行中的多个位单元的第一子集的第一读取字线，并且在第二读取操作期间断言第二读取字线 连接到所述多个位单元的第二子集，其中所述第一和第二子集位于同一行比特单元中。

    Memory timing circuit
    9.
    发明授权
    Memory timing circuit 有权
    存储器定时电路

    公开(公告)号：US09111589B2

    公开(公告)日：2015-08-18

    申请号：US14018404

    申请日：2013-09-04

    Applicant: QUALCOMM Incorporated

    Inventor： Rakesh Kumar Sinha ,  Chirag Gulati ,  Ritu Chaba ,  Sei Seung Yoon

    IPC: G11C7/00 ,  G11C7/06 ,  G11C7/04 ,  G11C7/08 ,  G11C7/22

    CPC classification number: G11C7/06 ,  G11C7/04 ,  G11C7/08 ,  G11C7/227

    Abstract: Disclosed are various apparatuses and methods for a memory with a multiple word line design. A memory timing circuit may include a dummy word line including a first portion and a second portion and further including capacitative loading that is lumped in the second portion of the dummy word line, a first transistor connected to the first portion of the dummy word line and configured to charge the dummy word line, and a second transistor connected to the second portion of the dummy word line and configured to discharge the dummy word line. A method may include charging a dummy word line using a first transistor, and discharging the dummy word line using a second transistor, wherein the dummy word line includes a first portion and a second portion and further includes capacitative loading that is lumped in the second portion of the dummy word line.

    Abstract translation: 公开了具有多字线设计的存储器的各种装置和方法。 存储器定时电路可以包括包括第一部分和第二部分的虚拟字线，并且还包括集中在伪字线的第二部分中的电容负载，连接到虚拟字线的第一部分的第一晶体管和 被配置为对所述虚拟字线充电;以及第二晶体管，连接到所述虚拟字线的第二部分，并且被配置为对所述虚拟字线进行放电。 一种方法可以包括使用第一晶体管对虚拟字线进行充电，以及使用第二晶体管对该虚拟字线进行放电，其中，所述虚拟字线包括第一部分和第二部分，并且还包括集中在所述第二部分中的电容负载 的虚拟字线。

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