公开(公告)号：US09947419B1

公开(公告)日：2018-04-17

申请号：US15472121

申请日：2017-03-28

申请人： QUALCOMM Incorporated

发明人： Rakesh Kumar Sinha ,  Priyankar Mathuria ,  Sharad Kumar Gupta

IPC分类号： G11C29/50 ,  G11C29/12 ,  G11C11/419

CPC分类号： G11C29/1201 ,  G11C11/419 ,  G11C29/02 ,  G11C29/32 ,  G11C2029/1204 ,  G11C2029/3202

摘要： A first bitline driver includes a multiplexer for outputting data and write mask signals in functional mode, and test vector signal in test mode; a latch to latch the data signal in functional mode and the test vector signal in test mode; a latch to latch the write mask signal in functional mode and the test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell based on the data signal. A second bitline driver includes a latch to latch a data signal in functional mode if a write mask signal is deasserted and to latch a test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell.

公开(公告)号：US10140044B2

公开(公告)日：2018-11-27

申请号：US15086943

申请日：2016-03-31

申请人： QUALCOMM Incorporated

发明人： Priyankar Mathuria ,  Rakesh Kumar Sinha ,  Gururaj Shamanna

IPC分类号： G06F3/06 ,  G11C7/10 ,  G11C8/12 ,  G11C11/419

摘要： In an aspect of the disclosure, a method and an apparatus are provided. The apparatus may be a memory. The memory may include a first memory portion configured to store a first bit and generate a first data bit output. The first data bit output may be a function of the first bit when a first read enable is active. The memory may also include a second memory portion configured to store a second bit and generate a second data bit output. The second data bit output may be a function of the second bit when a second read enable is active. The memory may include a switch configured to select between the first and second bits for a read operation based on the first and second data bit outputs.

公开(公告)号：US09875790B1

公开(公告)日：2018-01-23

申请号：US15476746

申请日：2017-03-31

申请人： QUALCOMM Incorporated

发明人： Rakesh Kumar Sinha ,  Priyankar Mathuria ,  Sharad Kumar Gupta ,  Lakshmikantha Holla Vakwadi

IPC分类号： G11C11/00 ,  G11C11/419 ,  G11C11/417

CPC分类号： G11C11/419 ,  G11C7/12 ,  G11C7/22 ,  G11C11/417 ,  G11C2207/229

摘要： A negative bit line boost circuit for a memory is configured to control a write multiplexer and a write assist transistor so that charge from a boost capacitor positively charges a bit line following a write assist period.

公开(公告)号：US09875776B1

公开(公告)日：2018-01-23

申请号：US15363401

申请日：2016-11-29

申请人： QUALCOMM Incorporated

发明人： Priyankar Mathuria ,  Rakesh Kumar Sinha ,  Sharad Kumar Gupta

IPC分类号： G11C7/00 ,  G11C7/12 ,  G11C7/10

CPC分类号： G11C7/1009 ,  G11C7/1084 ,  G11C2207/2227

摘要： Maskable level shifter circuits and memories are provided. Memories may include a plurality of memory cells and a bitline coupled to the plurality of memory cells. The memories includes a maskable level shifter configured to receive write data and a mask signal. A maskable level shifter includes a level shifter configured to level shift the write data and output the level shifted write data to the bitline when the mask signal is inactive and a masking circuit configured to remove power from the level shifter when the mask signal is active. Another maskable level shifter includes a level shifter configured to level shift the write data and output the level shifted write data to the bitline when the mask signal is inactive and a masking circuit configured to output a predetermined state to the bitline when the mask signal is active.

公开(公告)号：US09570158B1

公开(公告)日：2017-02-14

申请号：US15146070

申请日：2016-05-04

申请人： QUALCOMM Incorporated

发明人： Priyankar Mathuria ,  Gururaj Shamanna ,  VRC Krishna Teja Kunisetty

IPC分类号： G11C7/10 ,  G11C11/419 ,  H03K3/356 ,  H03K3/037

CPC分类号： G11C11/419 ,  G11C7/1051 ,  G11C7/106 ,  H03K3/356104

摘要： An integrated circuit (IC) is disclosed herein for accelerating memory access with an output latch. In an example aspect, the output latch includes a data storage unit, first circuitry, and second circuitry. The data storage unit includes a first input node configured to receive a first input voltage, a second input node configured to receive a second input voltage, a first output node configured to provide a first output voltage, and a second output node configured to provide a second output voltage. The first circuitry is configured to accelerate a voltage level transition of the first output voltage at the first output node responsive to the first input voltage at the first input node. The second circuitry is configured to accelerate a voltage level transition of the second output voltage at the second output node responsive to the second input voltage at the second input node.

摘要翻译： 本文公开了一种用于利用输出锁存器加速存储器存取的集成电路（IC）。 在示例方面，输出锁存器包括数据存储单元，第一电路和第二电路。 数据存储单元包括被配置为接收第一输入电压的第一输入节点，被配置为接收第二输入电压的第二输入节点，被配置为提供第一输出电压的第一输出节点和被配置为提供第一输出节点的第二输出节点 第二输出电压。 第一电路被配置为响应于第一输入节点处的第一输入电压来加速第一输出节点处的第一输出电压的电压电平转变。 第二电路被配置为响应于第二输入节点处的第二输入电压而加速第二输出节点处的第二输出电压的电压电平转变。