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公开(公告)号：US10163884B1
公开(公告)日：2018-12-25
申请号：US15667576
申请日：2017-08-02
Applicant: QUALCOMM Incorporated
Inventor： Harikrishna Chintarlapalli Reddy , Jonathan Holland , Sajin Mohamad
IPC: H01L27/02 , G06F17/50 , H03K19/00 , H01L27/118 , H03K19/177 , H01L23/522
Abstract: An IC includes an array of cells and a first set of endcap cells. The array of cells includes a first set of Mx layer power interconnects coupled to a first voltage, a first set of Mx layer interconnects, a second set of Mx layer power interconnects coupled to a second voltage source, and a second set of Mx layer interconnects. The first set of endcap cells includes first and second sets of Mx+1 layer interconnects. The first set of Mx+1 layer interconnects is coupled to the first set of Mx layer power interconnects and to the second set of Mx layer interconnects to provide a first set of decoupling capacitors. The second set of Mx+1 layer interconnects is coupled to the second set of Mx layer power interconnects and to the first set of Mx layer interconnects to provide a second set of decoupling capacitors.
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Patent Agency Ranking
公开(公告)号：US10978437B2
公开(公告)日：2021-04-13
申请号：US16456311
申请日：2019-06-28
Applicant: QUALCOMM Incorporated
IPC: H01L27/02 , H01L27/06 , H01L23/528 , H03K17/687 , H03F3/45 , H01L29/78 , H01L49/02
Abstract: An integrated circuit, comprising a transistor-based cell comprising a set of fin field effect transistors (Fin FETs) chained together in a first direction, wherein the set of Fin FETs include fins extending longitudinally along the first direction and equally-spaced apart in a second direction orthogonal to the first direction by a fin pitch, and a set of polysilicon gates extending longitudinally along the second direction and equally-spaced apart in the first direction by a poly pitch, wherein a first dimension of the transistor-based cell along the first direction is substantially a first integer multiplied by the poly pitch, and wherein a second dimension of the transistor-based cell along the second direction is substantially a second integer multiplied by the fin pitch. The integrated circuit may include other non-transistor-based cells (e.g., passive cells), such as thin-film resistor or capacitor cells, which are arranged in a two-dimensional array with the transistor-based cell.
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公开(公告)号：US11736105B1
公开(公告)日：2023-08-22
申请号：US17831306
申请日：2022-06-02
Applicant: QUALCOMM Incorporated
Inventor： Abhinav Murali , Pradeep Kumar Sana , Sajin Mohamad , Harikrishna Chintarlapalli Reddy , Rakesh Kumar Sinha , Jibu Varghese K
IPC: H03K17/687 , H04B1/40
CPC classification number: H03K17/6872 , H04B1/40
Abstract: An integrated circuit (IC), including: a current mirror, including: a first field effect transistor (FET) including a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET including a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET, and the second source is coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET.
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公开(公告)号：US11056253B2
公开(公告)日：2021-07-06
申请号：US16800949
申请日：2020-02-25
Applicant: QUALCOMM Incorporated
Inventor： Harikrishna Chintarlapalli Reddy , Alvin Leng Sun Loke
Abstract: An apparatus including a dielectric layer; and a set of thin-film resistors arranged in a row extending in a first direction on the dielectric layer, wherein lengths of the set of thin-film resistors in a second direction substantially orthogonal to the first direction are substantially the same, wherein the set of thin-film resistors includes a first subset of one or more thin-film resistors with respective terminals spaced apart by a first distance, and wherein the set of thin-film resistors includes a second subset of one or more thin-film resistors with respective terminals spaced apart by a second distance, the first distance being different than the second distance.
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公开(公告)号：US12057829B2
公开(公告)日：2024-08-06
申请号：US18336621
申请日：2023-06-16
Applicant: QUALCOMM Incorporated
Inventor： Abhinav Murali , Pradeep Kumar Sana , Sajin Mohamad , Harikrishna Chintarlapalli Reddy , Rakesh Kumar Sinha , Jibu Varghese K
IPC: H03K17/687 , H04B1/40
CPC classification number: H03K17/6872 , H04B1/40
Abstract: An integrated circuit (IC), including: a current mirror, including: a first field effect transistor (FET) including a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET including a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET, and the second source is coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET.
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公开(公告)号：US11424054B2
公开(公告)日：2022-08-23
申请号：US17334402
申请日：2021-05-28
Applicant: QUALCOMM INCORPORATED
Inventor： Harikrishna Chintarlapalli Reddy , Alvin Leng Sun Loke
Abstract: An apparatus including a dielectric layer; and a set of thin-film resistors arranged in a row extending in a first direction on the dielectric layer, wherein lengths of the set of thin-film resistors in a second direction substantially orthogonal to the first direction are substantially the same, wherein the set of thin-film resistors includes a first subset of one or more thin-film resistors with respective terminals spaced apart by a first distance, and wherein the set of thin-film resistors includes a second subset of one or more thin-film resistors with respective terminals spaced apart by a second distance, the first distance being different than the second distance.
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