公开(公告)号：US11736105B1

公开(公告)日：2023-08-22

申请号：US17831306

申请日：2022-06-02

Applicant: QUALCOMM Incorporated

Inventor： Abhinav Murali ,  Pradeep Kumar Sana ,  Sajin Mohamad ,  Harikrishna Chintarlapalli Reddy ,  Rakesh Kumar Sinha ,  Jibu Varghese K

IPC: H03K17/687 ,  H04B1/40

CPC classification number: H03K17/6872 ,  H04B1/40

Abstract: An integrated circuit (IC), including: a current mirror, including: a first field effect transistor (FET) including a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET including a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET, and the second source is coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET.

公开(公告)号：US11043948B1

公开(公告)日：2021-06-22

申请号：US16802684

申请日：2020-02-27

Applicant: QUALCOMM Incorporated

Inventor： Suresh Naidu Lekkala ,  Sajin Mohamad

IPC: H03K19/00 ,  H03F3/45 ,  H03K19/0185 ,  H03K19/003

Abstract: A bandwidth enhanced amplifier for high frequency CML To CMOS conversion is disclosed. In some implementations, an improved CML to CMOS converter includes a differential amplifier having a first and a second input transistors, and a first and a second load transistors. The first input transistor is coupled in series with the first load transistor, and the second input transistor is coupled in series with the second load transistor. The improved CML to CMOS converter further includes a first capacitor and a second capacitor. The first capacitor is coupled directly between a gate of the first input transistor and a gate of the first load transistor.

公开(公告)号：US10965383B1

公开(公告)日：2021-03-30

申请号：US16732570

申请日：2020-01-02

Applicant: QUALCOMM Incorporated

Inventor： Suresh Naidu Lekkala ,  Sajin Mohamad

IPC: H03K17/00 ,  H04B14/04 ,  H03K19/0185

Abstract: Certain aspects of the present disclosure generally relate to a sampling circuit, such as a sampling circuit for a low-voltage differential signaling (LVDS) serializer/deserializer (SerDes) system. One example sampling circuit generally includes a latching circuit and a plurality of pass-gate transistors. The latching circuit includes differential inputs, differential outputs, a clocked input circuit coupled to the differential inputs, a first cross-coupled circuit coupled to the clocked input circuit, and a second cross-coupled circuit coupled to the first cross-coupled circuit, wherein the first and second cross-coupled circuits are coupled to the differential outputs of the latching circuit. Each pass-gate transistor is coupled between one of the differential inputs of the latching circuit and a corresponding differential input of the sampling circuit.

公开(公告)号：US10163884B1

公开(公告)日：2018-12-25

申请号：US15667576

申请日：2017-08-02

Applicant: QUALCOMM Incorporated

Inventor： Harikrishna Chintarlapalli Reddy ,  Jonathan Holland ,  Sajin Mohamad

IPC: H01L27/02 ,  G06F17/50 ,  H03K19/00 ,  H01L27/118 ,  H03K19/177 ,  H01L23/522

Abstract: An IC includes an array of cells and a first set of endcap cells. The array of cells includes a first set of Mx layer power interconnects coupled to a first voltage, a first set of Mx layer interconnects, a second set of Mx layer power interconnects coupled to a second voltage source, and a second set of Mx layer interconnects. The first set of endcap cells includes first and second sets of Mx+1 layer interconnects. The first set of Mx+1 layer interconnects is coupled to the first set of Mx layer power interconnects and to the second set of Mx layer interconnects to provide a first set of decoupling capacitors. The second set of Mx+1 layer interconnects is coupled to the second set of Mx layer power interconnects and to the first set of Mx layer interconnects to provide a second set of decoupling capacitors.

公开(公告)号：US12057829B2

公开(公告)日：2024-08-06

申请号：US18336621

申请日：2023-06-16

Applicant: QUALCOMM Incorporated

Inventor： Abhinav Murali ,  Pradeep Kumar Sana ,  Sajin Mohamad ,  Harikrishna Chintarlapalli Reddy ,  Rakesh Kumar Sinha ,  Jibu Varghese K

IPC: H03K17/687 ,  H04B1/40

CPC classification number: H03K17/6872 ,  H04B1/40

Abstract: An integrated circuit (IC), including: a current mirror, including: a first field effect transistor (FET) including a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET including a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET, and the second source is coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET.

公开(公告)号：US09762228B2

公开(公告)日：2017-09-12

申请号：US14855238

申请日：2015-09-15

Applicant: QUALCOMM Incorporated

Inventor： Neha Agrawal ,  Sajin Mohamad ,  Chulkyu Lee

IPC: H03K21/00 ,  H03K7/06 ,  H03K19/21 ,  H03K3/037 ,  H03K21/10 ,  H03K23/64 ,  H03K23/00 ,  H03K21/02 ,  G06F1/08

CPC classification number: H03K7/06 ,  G06F1/08 ,  H03K3/037 ,  H03K19/21 ,  H03K21/00 ,  H03K21/026 ,  H03K21/10 ,  H03K23/00 ,  H03K23/64

Abstract: Systems and methods for dividing input clock signals by programmable divide ratios can produce output clock signals with the delay from the input clock signal to the output clock signal independent of the value of the divide ratio and with the duty cycle of the output clock signal being 50% independent of the value of the divide ratio. An example programmable clock divider includes a modulo N counter that produces a count signal that counts modulo the divide ratio and a half-rate clock signal generator that produces a common half-rate clock signal, an even half-rate clock signal, and an odd half-rate clock signal that toggle at one-half the rate of the output clock signal. The common half-rate clock signal, the even half-rate clock signal, and the odd half-rate clock signal are combined to produce the output clock signal.

公开(公告)号：US20170077918A1

公开(公告)日：2017-03-16

申请号：US14855238

申请日：2015-09-15

Applicant: QUALCOMM Incorporated

Inventor： Neha Agrawal ,  Sajin Mohamad ,  Chulkyu Lee

IPC: H03K7/06 ,  H03K3/037 ,  H03K19/21

CPC classification number: H03K7/06 ,  G06F1/08 ,  H03K3/037 ,  H03K19/21 ,  H03K21/00 ,  H03K21/026 ,  H03K21/10 ,  H03K23/00 ,  H03K23/64

Abstract: Systems and methods for dividing input clock signals by programmable divide ratios can produce output clock signals with the delay from the input clock signal to the output clock signal independent of the value of the divide ratio and with the duty cycle of the output clock signal being 50% independent of the value of the divide ratio. An example programmable clock divider includes a modulo N counter that produces a count signal that counts modulo the divide ratio and a half-rate clock signal generator that produces a common half-rate clock signal, an even half-rate clock signal, and an odd half-rate clock signal that toggle at one-half the rate of the output clock signal. The common half-rate clock signal, the even half-rate clock signal, and the odd half-rate clock signal are combined to produce the output clock signal.

Abstract translation: 通过可编程分频比对输入时钟信号进行分频的系统和方法可以产生输出时钟信号，输出时钟信号与输入时钟信号的延迟无关于分频比的值，输出时钟信号的占空比为50 ％独立于分频比的值。 示例性可编程时钟分频器包括模N计数器，其产生计数分频比的计数信号和产生公共半速率时钟信号的半速率时钟信号发生器，偶数半速率时钟信号和奇数 半速率时钟信号以输出时钟信号的一半速率切换。 公共半速时钟信号，偶数半速率时钟信号和奇数半速率时钟信号被组合以产生输出时钟信号。