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公开(公告)号：US09735787B2
公开(公告)日：2017-08-15
申请号：US14741984
申请日：2015-06-17
申请人： ANALOG DEVICES, INC.
发明人： Oscar Sebastian Burbano , Matthew D. McShea , Peter Derounian , Reuben P. Nelson , Ziwei Zheng , Brad P. Jeffries
CPC分类号： H03K23/40 , G06F1/022 , H03K21/00 , H03K21/38 , H03K23/00 , H03K23/58 , H03K23/662 , H03K23/665
摘要： An agile frequency synthesizer with dynamic phase and pulse-width control is disclosed. In one aspect, the frequency synthesizer includes a count circuit configured to modify a stored count value by an adjustment value. The frequency synthesizer also includes an output clock generator configured to generate an output clock signal having rising and falling edges that are based at least in part on the stored count value satisfying a count threshold. The count circuit is further configured to alter at least one of the period or phase of the output clock signal based at least in part on modifying an adjustment rate of the count circuit.
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公开(公告)号：US20160308536A1
公开(公告)日：2016-10-20
申请号：US15099753
申请日：2016-04-15
CPC分类号： H03K21/026 , G06F1/08 , G06F7/68 , H03K21/00 , H03K21/10 , H03K21/38 , H03K21/40 , H03K23/00 , H03K23/40 , H03K23/58 , H03K23/64 , H03K23/68 , H03L7/1974
摘要： Frequency divider techniques are disclosed which can be used to address two problems: when an incorrect division occurs if the modulus control changes before the divide cycle is complete, and when an incorrect division occurs due to a boundary crossing (e.g., power-of-2 boundary crossing in a fractional-N PLL application). In one embodiment, a frequency divider is provided comprising a plurality of flip-flops operatively coupled to carry out division of an input frequency, and configured to generate a modulus output and receive a divided clock signal of a previous cell. An additional flip-flop is selectively clocked off one of the modulus output or the divided clock of the previous stage, depending at least in part on a Skip control signal applied to a data input of the additional flip-flop, and is further configured to selectively reset the plurality of flip-flops to a state that will result in a correct divide ratio.
摘要翻译： 可以使用分频器技术来解决两个问题：如果模数控制在分频周期完成之前变化，并且当由于边界穿越而发生不正确的划分时（例如，功率2 在分数N PLL应用中的边界交叉）。 在一个实施例中，提供了一种分频器，其包括可操作地耦合以执行输入频率划分的多个触发器，并且被配置为产生模数输出并接收先前小区的分频时钟信号。 至少部分地基于施加到附加触发器的数据输入端的跳过控制信号，另外的触发器选择性地将时钟从先前级的模数输出或分频时钟中的一个计时，并进一步被配置为 有选择地将多个触发器复位到将导致正确分频比的状态。
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公开(公告)号：US20160233852A1
公开(公告)日：2016-08-11
申请号：US14617950
申请日：2015-02-10
申请人： Inayat Ali , Puneet Dodeja , Sachin Jain
发明人： Inayat Ali , Puneet Dodeja , Sachin Jain
CPC分类号： H03K3/017 , H03K5/1565 , H03K21/00 , H03K21/026 , H03K21/10 , H03K23/00 , H03K23/002
摘要： A divided clock signal is generated from an input clock signal. The duty cycle of the divided clock signal is programmed by generating a compare value based on values of duty cycle input and a divide value of the input clock signal. The compare value is compared to a count value to generate short and long pulse signals. The divided clock signal is generated based on the short and long pulse signals. The duty cycle of the divided clock signal varies in accordance with the compare value.
摘要翻译： 从输入时钟信号产生分频时钟信号。 通过基于占空比输入的值和输入时钟信号的除法产生比较值来编程分频时钟信号的占空比。 将比较值与计数值进行比较，以生成短和长脉冲信号。 基于短脉冲信号和长脉冲信号产生分频时钟信号。 分频时钟信号的占空比根据比较值而变化。
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4.发明申请公开(公告)号：US20160072509A1
公开(公告)日：2016-03-10
申请号：US14805178
申请日：2015-07-21
发明人： Hailong JIA
IPC分类号： H03K21/02
CPC分类号： H03K21/026 , G06F1/08 , H03K21/00 , H03K21/023 , H03K21/38 , H03K23/00 , H03K23/586 , H03L7/193 , H03L7/1974
摘要： A multi-modulus frequency divider includes a frequency division module, a frequency selection module, and a retiming module. The frequency division module is configured to receive an input signal and perform mufti-mode frequency processing on the input signal, so as to generate and output a plurality of divided signals to the frequency selection module. The frequency selection module is configured to receive the plurality of divided signals from the frequency division module, select a divided signal having a desired frequency from among the plurality of divided signals, and output the selected divided signal to the retiming module. The retiming module is configured to receive the selected divided signal from the frequency selection module, perform a retiming operation on the selected divided signal, and output a retimed selected divided signal.
摘要翻译： 多模式分频器包括分频模块，频率选择模块和重定时模块。 分频模块被配置为接收输入信号并对输入信号执行多模式频率处理，以便产生并输出多个分频信号给频率选择模块。 频率选择模块被配置为从分频模块接收多个分频信号，从多个分频信号中选择具有期望频率的分频信号，并将选择的分频信号输出到重定时模块。 重定时模块被配置为从频率选择模块接收所选择的分频信号，对选择的分频信号执行重新定时操作，并输出重新定时的选择的分频信号。
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公开(公告)号：US20150010124A1
公开(公告)日：2015-01-08
申请号：US13935552
申请日：2013-07-04
申请人： Naman Gupta , Amol Agarwal , Gaurav Goyal
发明人： Naman Gupta , Amol Agarwal , Gaurav Goyal
IPC分类号： H03K23/40
摘要： An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower order counter sub-module. The control logic is arranged to clock gate at least one higher order counter sub-module dependent on a logical combination of outputs of the lower order counter sub-module and where the control logic uses pipelining to store at least one previous control logic output for use in determining a later control logic output.
摘要翻译： n位计数器由级联计数器子模块形成。 计数器包括耦合到低阶计数器子模块的组合控制逻辑。 控制逻辑被配置为根据低阶计数器子模块的输出的逻辑组合对至少一个更高阶计数器子模块进行时钟门控，并且其中控制逻辑使用流水线存储至少一个先前控制逻辑输出以供使用 在确定稍后的控制逻辑输出时。
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公开(公告)号：US20130182817A1
公开(公告)日：2013-07-18
申请号：US13738476
申请日：2013-01-10
发明人： Yasushi IMAI
IPC分类号： H03K23/00
摘要： The timing generation circuit includes a binary counter constituted of three T-flip-flop circuits, and a binary state at reset of the binary counter is also used at system reset and in generation of the output pulses, to generate eight output pulses having different timings from eight binary states generated by the binary counter and including the state at the reset. At the system reset, a reset signal to the binary counter is delayed, so that an output of a decoder circuit at the reset of the binary counter is delayed. Therefore, the output of the decoder circuit is masked with a fast reset signal, so that the output of the decoder circuit at the system reset can be prevented from being reflected in an output terminal.
摘要翻译： 定时生成电路包括由三个T触发器电路构成的二进制计数器，并且二进制计数器的复位时的二进制状态也用于系统复位和产生输出脉冲，以产生具有不同定时的八个输出脉冲 由二进制计数器产生的8个二进制状态，并包括复位状态。 在系统复位时，二进制计数器的复位信号被延迟，使得在二进制计数器的复位时解码器电路的输出被延迟。 因此，解码器电路的输出被快速复位信号屏蔽，从而可以防止在系统复位时解码器电路的输出反映在输出端子中。
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公开(公告)号：US07888983B2
公开(公告)日：2011-02-15
申请号：US12558278
申请日：2009-09-11
申请人： Kun Zhang , Kenneth C. Barnett
发明人： Kun Zhang , Kenneth C. Barnett
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K21/38 , H03K23/00
摘要： Techniques for generating a signal having a predetermined duty cycle. In an exemplary embodiment, a first counter is configured to count a first number of cycles of an oscillator signal, and a second counter is configured to count a second number of cycles of the oscillator signal, with the second number being greater than the first number. The output of the second counter is used to reset the first and second counters, while the outputs of the first and second counters further drive a toggle latch for generating the signal having predetermined duty cycle. Further aspects include techniques for accommodating odd and even values for the second number.
摘要翻译： 用于产生具有预定占空比的信号的技术。 在示例性实施例中，第一计数器被配置为对振荡器信号的第一数量的周期进行计数，并且第二计数器被配置为对振荡器信号的第二数量的周期进行计数，其中第二数量大于第一数量 。 第二计数器的输出用于复位第一和第二计数器，而第一和第二计数器的输出进一步驱动用于产生具有预定占空比的信号的触发锁存器。 另外的方面包括用于适应第二数量的奇数和偶数值的技术。
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公开(公告)号：US20100327929A1
公开(公告)日：2010-12-30
申请号：US12558278
申请日：2009-09-11
申请人： Kun Zhang , Kenneth C. Barnett
发明人： Kun Zhang , Kenneth C. Barnett
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K21/38 , H03K23/00
摘要： Techniques for generating a signal having a predetermined duty cycle. In an exemplary embodiment, a first counter is configured to count a first number of cycles of an oscillator signal, and a second counter is configured to count a second number of cycles of the oscillator signal, with the second number being greater than the first number. The output of the second counter is used to reset the first and second counters, while the outputs of the first and second counters further drive a toggle latch for generating the signal having predetermined duty cycle. Further aspects include techniques for accommodating odd and even values for the second number.
摘要翻译： 用于产生具有预定占空比的信号的技术。 在示例性实施例中，第一计数器被配置为对振荡器信号的第一数量的周期进行计数，并且第二计数器被配置为对振荡器信号的第二数量的周期进行计数，其中第二数量大于第一数量 。 第二计数器的输出用于复位第一和第二计数器，而第一和第二计数器的输出进一步驱动用于产生具有预定占空比的信号的触发锁存器。 另外的方面包括用于适应第二数量的奇数和偶数值的技术。
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公开(公告)号：US07323913B1
公开(公告)日：2008-01-29
申请号：US11871578
申请日：2007-10-12
申请人： Marcel A. Kossel
发明人： Marcel A. Kossel
IPC分类号： H03K21/00
CPC分类号： H03K23/00
摘要： A multiphase divider includes a plurality of resetable dividers configured for performing resetable divider stages to a plurality of multiphase signals forming a plurality of divided multiphase signals having a monotonic increasing phase with equal spacing and an ideal duty cycle of 50%, wherein the plurality of divided multiphase signals have no phase ambiguity; and a reset signal generator configured for producing a plurality of periodic reset signals to the plurality of resetable dividers to enable the plurality of resetable dividers to divide the plurality of multiphase signals in a timely correct sequence to form the divided multiphase signal, the plurality of periodic reset signals being produced by a combinational network of the reset signal generator, the combinational network is configured for generating a number of pulses based on the plurality of multiphase signals and performing decimation stages to reduce the number of pulses within the pulse traces.
摘要翻译： 多相分配器包括多个可复位分配器，其被配置用于对多个多相信号执行可复位分频器级，所述多相信号形成具有等间距的单调增加相位和50％的理想占空比的多个分频多相信号，其中多个分频 多相信号没有相位模糊; 以及复位信号发生器，被配置为产生多个周期性复位信号到多个可复位分频器，以使得多个可复位分频器可以及时正确的顺序划分多个多相信号以形成分频多相信号，多个周期性 复位信号由复位信号发生器的组合网络产生，组合网络被配置为基于多个多相信号产生多个脉冲，并执行抽取级以减少脉冲迹线内的脉冲数。
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公开(公告)号：US20040155684A1
公开(公告)日：2004-08-12
申请号：US10772788
申请日：2004-02-05
申请人： Xilinx, Inc.
发明人： Andy T. Nguyen
IPC分类号： H03K021/00
摘要： A digital frequency synthesizer (DFS) circuit adds little additional delay on the clock path. True and complement versions of an input clock signal are provided to a first and second passgates, respectively. Under the direction of a control circuit, the passgates pass selected rising edges of the true clock signal, and selected falling edges of the complement clock signal, to an output clock terminal of the DFS circuit. When neither the true nor the complement clock signal is passed, a keeper circuit retains the value already present at the output clock terminal. In some embodiments, both passgates can be disabled and a ground or power high signal can be applied to the output terminal. Other embodiments include PLDs in which the DFS circuits are employed to allow individual clock control for each programmable logic block.
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