公开(公告)号：US20130182817A1

公开(公告)日：2013-07-18

申请号：US13738476

申请日：2013-01-10

申请人： Seiko Instruments Inc.

发明人： Yasushi IMAI

IPC分类号： H03K23/00

CPC分类号： H03K23/00 ,  H03K23/42

摘要： The timing generation circuit includes a binary counter constituted of three T-flip-flop circuits, and a binary state at reset of the binary counter is also used at system reset and in generation of the output pulses, to generate eight output pulses having different timings from eight binary states generated by the binary counter and including the state at the reset. At the system reset, a reset signal to the binary counter is delayed, so that an output of a decoder circuit at the reset of the binary counter is delayed. Therefore, the output of the decoder circuit is masked with a fast reset signal, so that the output of the decoder circuit at the system reset can be prevented from being reflected in an output terminal.

摘要翻译： 定时生成电路包括由三个T触发器电路构成的二进制计数器，并且二进制计数器的复位时的二进制状态也用于系统复位和产生输出脉冲，以产生具有不同定时的八个输出脉冲 由二进制计数器产生的8个二进制状态，并包括复位状态。 在系统复位时，二进制计数器的复位信号被延迟，使得在二进制计数器的复位时解码器电路的输出被延迟。 因此，解码器电路的输出被快速复位信号屏蔽，从而可以防止在系统复位时解码器电路的输出反映在输出端子中。