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公开(公告)号：US09893875B2
公开(公告)日：2018-02-13
申请号：US15270444
申请日：2016-09-20
Applicant: QUALCOMM Incorporated
Inventor： Marco Zanuso , Mohammad Elbadry , Tsai-Pi Hung , Ravi Sridhara , Francesco Gatta , Jingcheng Zhuang
CPC classification number: H04L7/033 , H03L7/14 , H03L7/143 , H03L7/1976 , H03L2207/08 , H04L5/14 , H04L69/28 , H04W84/042
Abstract: A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.
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公开(公告)号：US10026685B2
公开(公告)日：2018-07-17
申请号：US14866111
申请日：2015-09-25
Applicant: QUALCOMM Incorporated
Inventor： Zhang Jin , Tao Yang , Tsai-Pi Hung , Mohammad Farazian
IPC: H01L23/522 , H03H7/00 , H01L23/528
Abstract: Metal-oxide-metal (MOM) type capacitors include a first terminal configured to receive a first voltage, the first terminal being formed on a first dielectric layer; a first set of fingers formed on the first dielectric layer, the first set of fingers being coupled to the first terminal via a conductive trace formed on a second dielectric layer; a second terminal configured to receive second voltage, the second terminal being formed on the first dielectric layer; and a second set of fingers formed on the first dielectric layer, the second set of fingers being coupled to the second terminal, wherein the fingers of the second set are interspersed with the fingers of the first set.
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公开(公告)号：US09059733B2
公开(公告)日：2015-06-16
申请号：US13893099
申请日：2013-05-13
Applicant: QUALCOMM Incorporated
Inventor： Chiewcharn Narathong , Jong Min Park , Tsai-Pi Hung
CPC classification number: H03M1/66 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03G11/008 , H03L7/093 , H03L7/099 , H03L2207/06 , H03M1/664 , H03M1/765
Abstract: A circuit includes a digital-to-analog converter with non-uniform resolution for converting a digital signal into an analog signal. The digital-to-analog converter includes high-resolution circuitry, reduced-resolution circuitry coupled to the high-resolution circuitry and a switch coupled to the high-resolution circuitry and to the reduced-resolution circuitry. The switch couples one of the high-resolution circuitry and the reduced-resolution circuitry to an output node. The circuit also includes a decoder coupled to the switch. The decoder receives the digital signal to control the switch.
Abstract translation: 电路包括具有用于将数字信号转换为模拟信号的非均匀分辨率的数模转换器。 数模转换器包括高分辨率电路，耦合到高分辨率电路的低分辨率电路和耦合到高分辨率电路和降低分辨率电路的开关。 该开关将高分辨率电路和降低分辨率电路之一耦合到输出节点。 电路还包括耦合到开关的解码器。 解码器接收数字信号以控制开关。
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公开(公告)号：US11726513B2
公开(公告)日：2023-08-15
申请号：US17443093
申请日：2021-07-20
Applicant: QUALCOMM Incorporated
Inventor： Yung-Chung Lo , Gang Zhang , Yiping Han , Frederic Bossu , Tsai-Pi Hung , Jae-Hong Chang
CPC classification number: G05F1/575 , H02M3/156 , H02M1/0077
Abstract: A method, an apparatus, and a computer program product are provided. The apparatus may be a regulator circuit. The regulator circuit includes a first voltage regulator to regulate a first input voltage to the first voltage regulator, the first voltage regulator including a P-type metal-oxide-semiconductor (PMOS), a second voltage regulator to regulate a second input voltage to the second voltage regulator, and a switch circuit to selectively activate at least one of the first voltage regulator or the second voltage regulator. In one aspect, the second voltage regulator includes an N-type metal-oxide-semiconductor (NMOS). In one aspect, the second voltage regulator comprises a two-stage operational transconductance amplifier (OTA) circuit. In an aspect, the first voltage regulator is coupled to the second voltage regulator.
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公开(公告)号：US20170093362A1
公开(公告)日：2017-03-30
申请号：US14866111
申请日：2015-09-25
Applicant: QUALCOMM Incorporated
Inventor： Zhang Jin , Tao Yang , Tsai-Pi Hung , Mohammad Farazian
IPC: H03H7/00 , H01L23/528 , H01L23/522
CPC classification number: H01L23/5223 , H01L23/5227 , H01L23/5286 , H03H7/004
Abstract: Metal-oxide-metal (MOM) type capacitors include a first terminal configured to receive a first voltage, the first terminal being formed on a first dielectric layer; a first set of fingers formed on the first dielectric layer, the first set of fingers being coupled to the first terminal via a conductive trace formed on a second dielectric layer; a second terminal configured to receive second voltage, the second terminal being formed on the first dielectric layer; and a second set of fingers formed on the first dielectric layer, the second set of fingers being coupled to the second terminal, wherein the fingers of the second set are interspersed with the fingers of the first set.
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Patent Agency Ranking
6.发明授权Bias techniques and circuit arrangements to reduce leakage current in a circuit 有权偏置技术和电路布置，以减少电路中的漏电流公开(公告)号：US09488996B2
公开(公告)日：2016-11-08
申请号：US14691461
申请日：2015-04-20
Applicant: QUALCOMM Incorporated
CPC classification number: G05F1/46 , H01L27/0251 , H01L27/0255 , H01L27/0266 , H02H9/045 , H02H9/046
Abstract: An apparatus includes an input/output (I/O) pin and an electrostatic discharge device. The electrostatic discharge device is coupled to the I/O pin and to a voltage regulator.
Abstract translation: 一种装置包括输入/输出（I / O）引脚和静电放电装置。 静电放电装置耦合到I / O引脚和电压调节器。
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公开(公告)号：US11095216B2
公开(公告)日：2021-08-17
申请号：US14630506
申请日：2015-02-24
Applicant: QUALCOMM Incorporated
Inventor： Yung-Chung Lo , Gang Zhang , Yiping Han , Frederic Bossu , Tsai-Pi Hung , Jae-Hong Chang
Abstract: A method, an apparatus, and a computer program product are provided. The apparatus may be a regulator circuit. The regulator circuit includes a first voltage regulator to regulate a first input voltage to the first voltage regulator, the first voltage regulator including a P-type metal-oxide-semiconductor (PMOS), and a second voltage regulator to regulate a second input voltage to the second voltage regulator, the second voltage regulator including an N-type metal-oxide-semiconductor (NMOS). In an aspect, the first voltage regulator is coupled to the second voltage regulator.
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公开(公告)号：US10291242B1
公开(公告)日：2019-05-14
申请号：US15993254
申请日：2018-05-30
Applicant: QUALCOMM Incorporated
Inventor： Mohammad Elbadry , Marco Zanuso , Tsai-Pi Hung , Francesco Gatta , Yunliang Zhu
Abstract: Certain aspects of the present disclosure generally relate to techniques and circuits for phase correction, or at least adjustment, of multiple local-oscillator (LO) signals. For example, certain aspects provide an apparatus for phase adjustment. The apparatus generally includes a phase-locked loop (PLL), at least one frequency divider coupled to an output of the PLL, the at least one first frequency divider being external to the PLL, a phase adjustment circuit having an input coupled to an output of the frequency divider, and at least one mixer having an input coupled to at least one output of the phase adjustment circuit.
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公开(公告)号：US20180367135A1
公开(公告)日：2018-12-20
申请号：US15624744
申请日：2017-06-16
Applicant: QUALCOMM INCORPORATED
Inventor： Hung-Chuan Pai , Tsai-Pi Hung
Abstract: A switched capacitance circuit selectively provides a capacitance across first and second output nodes in response to a selection control signal. The switched capacitance circuit may include a first capacitor coupled between the first output node and a mid-node, a second capacitor coupled between the second output node and the mid-node, and a switching circuit. The switching circuit is configured to switch the first and second capacitors in response to the selection control signal and to provide a bias voltage at the mid-node in response to the selection control signal.
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公开(公告)号：US10063366B2
公开(公告)日：2018-08-28
申请号：US15269320
申请日：2016-09-19
Applicant: QUALCOMM Incorporated
Inventor： Marco Zanuso , Giovanni Marucci , Tsai-Pi Hung , Francesco Gatta , Bo Sun
CPC classification number: H04L7/0331 , H03L7/08 , H03L7/087 , H03L7/099 , H03L7/113 , H03L7/1974 , H03L7/1976 , H03L2207/06 , H04B1/40 , H04B1/713 , H04B2201/71353 , H04W72/0453
Abstract: A fast frequency hopping implementation in a phase lock loop (PLL) circuit achieves a PLL lock to a new frequency in a very short period of time. In one instant, frequency allocation at a transceiver is changed. In response, a local oscillator frequency hops to a new center frequency based on the changed frequency allocation. The hopping to the new center frequency is based on two-point modulation of a phase locked loop.
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