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公开(公告)号：US10819303B1
公开(公告)日：2020-10-27
申请号：US16656310
申请日：2019-10-17
Applicant: QUALCOMM Incorporated
Inventor： Joung Won Park , Bo Sun
Abstract: In certain aspects, an amplifier includes a first transistor including a gate, a drain, and a source, wherein the gate of the first transistor is coupled to a first input of the amplifier. The amplifier also includes a second transistor including a gate, a drain, and a source, wherein the gate of the second transistor is coupled to a second input of the amplifier. The amplifier further includes a first signal path coupled between the first input of the amplifier and the source of the second transistor, a second signal path coupled between the second input of the amplifier and the source of the first transistor, a first load coupled to the drain of the first transistor, and a second load coupled to the drain of the second transistor.
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公开(公告)号：US20190123887A1
公开(公告)日：2019-04-25
申请号：US15788615
申请日：2017-10-19
Applicant: QUALCOMM Incorporated
Inventor： Bo Sun
Abstract: In certain aspects of the present disclosure, a chip includes a signal driver having an output coupled to a terminal of a bidirectional link, wherein the signal driver is configured to transmit a first signal to another chip via the bidirectional link. The chip also includes a replica driver configured to generate a replica echo signal, a receiver having a first input coupled to the terminal of the bidirectional link and a second input coupled to the replica driver, and a tunable load coupled between the replica driver and the second input of the receiver. The receiver is configured to receive a second signal at the first input, to receive the replica echo signal at the second input, and to subtract the replica echo signal from the second signal.
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公开(公告)号：US09081396B2
公开(公告)日：2015-07-14
申请号：US13802725
申请日：2013-03-14
Applicant: QUALCOMM Incorporated
Inventor： Bo Sun
CPC classification number: G05F3/08 , G01R15/04 , G01R15/08 , G01R15/09 , G01R19/16519 , G01R19/16552 , G05F1/465
Abstract: A voltage divider circuit is provided that automatically and dynamically adjusts its voltage divider chains as a supply voltage changes. The voltage divider circuit includes a plurality of voltage divider branches having different divider factors to divide the supply voltage and obtain a divided supply voltage. Additionally, a control circuit is coupled to the plurality of voltage divider branches and adapted to automatically monitor the supply voltage and dynamically select a voltage divider branch from among the plurality of voltage divider branches to maintain a selected divided supply voltage within a pre-determined voltage range.
Abstract translation: 提供了一个分压电路，可以随着电源电压的变化自动动态地调节分压器的电压。 分压器电路包括具有不同分频器因数的多个分压器分支，以分割电源电压并获得分开的电源电压。 此外，控制电路耦合到多个分压器分支并且适于自动监测电源电压并且从多个分压器分支中动态地选择分压器分支，以将所选择的分压电源电压维持在预定电压内 范围。
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4.发明申请公开(公告)号：US20150015343A1
公开(公告)日：2015-01-15
申请号：US13938727
申请日：2013-07-10
Applicant: QUALCOMM Incorporated
Inventor： Gary John Ballantyne , Bo Sun , Yi Tang , Zixiang Yang , Masoud Ensafdaran
IPC: H03L7/099
CPC classification number: H03L7/0991 , H03B5/1265 , H03B2200/0088 , H03B2201/025 , H03B2202/017 , H03J5/24 , H03J2200/10 , H03J2200/36 , H03L7/099 , H03L2207/50
Abstract: One feature pertains to a digitally controlled oscillator (DCO) that comprises a variable capacitor and noise reduction circuitry. The variable capacitor has a variable capacitance value that controls an output frequency of the DCO. The variable capacitance value is based on a first bank capacitance value provided by a first capacitor bank, a second bank capacitance value provided by a second capacitor bank, and an auxiliary bank capacitance value provided by an auxiliary capacitor bank. The noise reduction circuitry is adapted to adjust the variable capacitance value by adjusting the auxiliary bank capacitance value while maintaining at least one of the first bank capacitance value and/or the second bank capacitance value substantially unchanged. Prior to adjusting the variable capacitance value, the noise reduction circuitry may determine that a received input DCO control word transitions across a capacitor bank sensitive boundary.
Abstract translation: 一个特征涉及包含可变电容器和降噪电路的数字控制振荡器（DCO）。 可变电容器具有控制DCO的输出频率的可变电容值。 可变电容值基于由第一电容器组提供的第一组电容值，由第二电容器组提供的第二组电容值和由辅助电容器组提供的辅助组电容值。 噪声降低电路适于通过调整辅助电容电容值来调节可变电容值，同时保持第一组电容值和/或第二组电容值中的至少一个基本上不变。 在调整可变电容值之前，噪声降低电路可以确定接收的输入DCO控制字在电容器组敏感边界之间转变。
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5.发明申请公开(公告)号：US20180241403A1
公开(公告)日：2018-08-23
申请号：US15436930
申请日：2017-02-20
Applicant: QUALCOMM Incorporated
Inventor： Bo Sun
CPC classification number: H03L7/087 , H03L7/0812 , H03L2207/12
Abstract: Multi-phase clock generation employing phase error detection between multiple delay circuit outputs in a controlled delay line to provide error correction is disclosed. A multi-phase clock generator is provided that includes a controlled delay line and a phase error detector circuit. Tap nodes are provided from outputs of one or more delay circuits in the controlled delay line. To detect and correct for phase errors in the controlled delay line, a phase detection circuit is provided that includes at least two phase detectors each configured to measure a phase offset error between tap nodes from the delay circuit(s) in the controlled delay line. These phase errors are then combined to create an error correction signal, which is used to control the delay of the delay circuit(s) in the controlled delay line to lock the phase of the output of the final delay circuit to an input reference clock signal.
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Patent Agency Ranking
公开(公告)号：US08957712B2
公开(公告)日：2015-02-17
申请号：US13842481
申请日：2013-03-15
Applicant: QUALCOMM Incorporated
CPC classification number: H03M1/50 , G04F10/005 , H03L7/08 , H03L7/0991 , H03L2207/50
Abstract: A time-to-digital converter converts the difference between transition times of a reference clock signal and an oscillating signal to a digital signal whose value is proportional to the transitions timing difference. The time-to-digital converter includes an edge detector, a time-to-voltage converter, and an analog-to-digital converter. The edge detector is adapted to detect, during each period of the reference clock signal, the edge (transition) of the oscillating signal that is closest to the edge of the reference clock signal. The time-to-voltage converter is adapted to generate an analog signal proportional to a difference in time between the detected edge of the oscillating signal and the edge of the reference clock signal. The analog-to-digital converter is adapted to convert the analog signal to a digital signal whose value is proportional the difference between the occurrence of the detected edge of the oscillating signal and the edge of the reference clock signal.
Abstract translation: 时间 - 数字转换器将参考时钟信号和振荡信号的转换时间之间的差异转换成数值信号，其数值信号与转换时序差成比例。 该时间 - 数字转换器包括边缘检测器，时间 - 电压转换器和模 - 数转换器。 边缘检测器适于在参考时钟信号的每个周期期间检测最靠近参考时钟信号的边缘的振荡信号的边沿（跃迁）。 时间 - 电压转换器适于产生与所检测的振荡信号的边沿与基准时钟信号的边沿之间的时间差成比例的模拟信号。 模拟 - 数字转换器适于将模拟信号转换成数字信号，该数字信号的值与振荡信号的检测到的边沿的出现与参考时钟信号的边沿之间的差成比例。
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公开(公告)号：US20140266353A1
公开(公告)日：2014-09-18
申请号：US13842481
申请日：2013-03-15
Applicant: QUALCOMM INCORPORATED
CPC classification number: H03M1/50 , G04F10/005 , H03L7/08 , H03L7/0991 , H03L2207/50
Abstract: A time-to-digital converter converts the difference between transition times of a reference clock signal and an oscillating signal to a digital signal whose value is proportional to the transitions timing difference. The time-to-digital converter includes an edge detector, a time-to-voltage converter, and an analog-to-digital converter. The edge detector is adapted to detect, during each period of the reference clock signal, the edge (transition) of the oscillating signal that is closest to the edge of the reference clock signal. The time-to-voltage converter is adapted to generate an analog signal proportional to a difference in time between the detected edge of the oscillating signal and the edge of the reference clock signal. The analog-to-digital converter is adapted to convert the analog signal to a digital signal whose value is proportional the difference between the occurrence of the detected edge of the oscillating signal and the edge of the reference clock signal.
Abstract translation: 时间 - 数字转换器将参考时钟信号和振荡信号的转换时间之间的差异转换成数值信号，其数值信号与转换时序差成比例。 该时间 - 数字转换器包括边缘检测器，时间 - 电压转换器和模 - 数转换器。 边缘检测器适于在参考时钟信号的每个周期期间检测最靠近参考时钟信号的边缘的振荡信号的边沿（跃迁）。 时间 - 电压转换器适于产生与所检测的振荡信号的边沿与基准时钟信号的边沿之间的时间差成比例的模拟信号。 模拟 - 数字转换器适于将模拟信号转换成数字信号，该数字信号的值与振荡信号的检测到的边沿的出现与参考时钟信号的边沿之间的差成比例。
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公开(公告)号：US20140266127A1
公开(公告)日：2014-09-18
申请号：US13802725
申请日：2013-03-14
Applicant: QUALCOMM INCORPORATED
Inventor： Bo Sun
IPC: G05F3/08
CPC classification number: G05F3/08 , G01R15/04 , G01R15/08 , G01R15/09 , G01R19/16519 , G01R19/16552 , G05F1/465
Abstract: A voltage divider circuit is provided that automatically and dynamically adjusts its voltage divider chains as a supply voltage changes. The voltage divider circuit includes a plurality of voltage divider branches having different divider factors to divide the supply voltage and obtain a divided supply voltage. Additionally, a control circuit is coupled to the plurality of voltage divider branches and adapted to automatically monitor the supply voltage and dynamically select a voltage divider branch from among the plurality of voltage divider branches to maintain a selected divided supply voltage within a pre-determined voltage range.
Abstract translation: 提供了一个分压电路，可以随着电源电压的变化自动动态地调节分压器的电压。 分压器电路包括具有不同分频器因数的多个分压器分支，以分割电源电压并获得分开的电源电压。 此外，控制电路耦合到多个分压器分支并且适于自动监测电源电压并且从多个分压器分支中动态地选择分压器分支，以将所选择的分压电源电压维持在预定电压内 范围。
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公开(公告)号：US11626865B1
公开(公告)日：2023-04-11
申请号：US17481666
申请日：2021-09-22
Applicant: QUALCOMM Incorporated
Inventor： Jianwen Ye , Bo Sun , Cheng Zhong
Abstract: A low-power clock generation circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts, a phase rotator circuit that outputs phase-adjusted clock signals, a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference, and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.
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公开(公告)号：US10749481B2
公开(公告)日：2020-08-18
申请号：US15956026
申请日：2018-04-18
Applicant: QUALCOMM Incorporated
Inventor： Bo Sun , Yi Tang , Daniel Butterfield
Abstract: Aspects generally relate to reducing delay, or phase jitter, in high speed signals transmission. Variations in power supply to ground potential changes the amount of delay introduced by transmit circuitry into the signal being transmitted, resulting in jitter, or phase noise, in the transmitted signal. To reduce phase jitter, or phase noise, aspects disclosed include a variable impedance circuit coupled to the signal distribution network, the impedance level of the variable impedance circuit is adjusted in response to variation in the supply to ground potential, such that the delay introduced by the impedance compensates for changes in the delay due to variations in supply to ground potential, resulting in substantially constant delay.
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