公开(公告)号：US10534047B2

公开(公告)日：2020-01-14

申请号：US15474339

申请日：2017-03-30

Applicant: QUALCOMM Incorporated

Inventor： Wei-Chuan Chen ,  Wah Nam Hsu ,  Xia Li ,  Seung Hyuk Kang ,  Nicholas Ka Ming Stevens-Yu

IPC: G01R33/09 ,  H01L43/08 ,  H01L27/22 ,  G01R33/12

Abstract: Tunnel magneto-resistive (TMR) sensors employing TMR devices with different magnetic field sensitivities for increased detection sensitivity are disclosed. For example, a TMR sensor may be used as a biosensor to detect the presence of biological materials. In aspects disclosed herein, free layers of at least two TMR devices in a TMR sensor are fabricated to exhibit different magnetic properties from each other (e.g., MR ratio, magnetic anisotropy, coercivity) so that each TMR device will exhibit a different change in resistance to a given magnetic stray field for increased magnetic field detection sensitivity. For example, the TMR devices may be fabricated to exhibit different magnetic properties such that one TMR device exhibits a greater change in resistance in the presence of a smaller magnetic stray field, and another TMR device exhibits a greater change in resistance in the presence of a larger magnetic stray field.

公开(公告)号：US10381060B2

公开(公告)日：2019-08-13

申请号：US15247791

申请日：2016-08-25

Applicant: QUALCOMM Incorporated

Inventor： Jimmy Jianan Kan ,  Chando Park ,  Peiyuan Wang ,  Sungryul Kim ,  Seung Hyuk Kang

IPC: G11C11/16 ,  H01L27/22

Abstract: A magnetic random access memory (MRAM) array including several bit cells is described. Each of the bit cells may include a perpendicular magnetic tunnel junction (pMTJ) including a reference layer, a barrier layer supporting the reference layer, and a free layer supporting the barrier layer. A spin-hall conductive material layer may support the free layer. A driver may be operable to set a state of at least one of the bit cells using an increased spin-transfer torque (STT) current and a spin-hall effect from the spin-hall conductive material layer. The increased STT current may be driven through the spin-hall conductive material layer and the pMTJ so that a spin current is generated from the reference layer and the spin-hall conductive material layer.

公开(公告)号：US20190147930A1

公开(公告)日：2019-05-16

申请号：US16247247

申请日：2019-01-14

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Wei-Chuan Chen ,  Wah Nam Hsu ,  Seung Hyuk Kang

IPC: G11C11/16 ,  H01L43/08 ,  G11C11/15 ,  H01F10/32

Abstract: Varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to facilitate use of MRAM for different memory applications is disclosed. In one aspect, energy barriers of MTJs in different MRAM arrays are varied. The energy barrier of an MTJ affects its write performance as the amount of switching current required to switch the magnetic orientation of a free layer of the MTJ is a function of its energy barrier. Thus, by varying the energy barriers of the MTJs in different MRAM arrays in a semiconductor die, different MRAM arrays may be used for different types of memory provided in the semiconductor die while still achieving distinct performance specifications. The energy barrier of an MTJ can be varied by varying the materials, heights, widths, and/or other characteristics of MTJ stacks.

公开(公告)号：US10263645B2

公开(公告)日：2019-04-16

申请号：US15716451

申请日：2017-09-26

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook Jung ,  Sara Choi ,  Byung Kyu Song ,  Taehui Na ,  Jisu Kim ,  Jung Pill Kim ,  Sungryul Kim ,  Taehyun Kim ,  Seung Hyuk Kang

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/15

Abstract: In an embodiment, an error detection and correction apparatus includes a positive edge triggered flip-flop that receives syndrome input based on a syndrome output a syndrome generator indicating whether or not input data includes an error, whereby the positive edge triggered flip-flop further provides a syndrome output to an error location decoder.

公开(公告)号：US20190088309A1

公开(公告)日：2019-03-21

申请号：US15709709

申请日：2017-09-20

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Venkat Rangan ,  Rashid Ahmed Akbar Attar ,  Nicholas Ka Ming Stevens-Yu

IPC: G11C11/419 ,  G11C11/56

CPC classification number: G11C11/419 ,  G11C7/1006 ,  G11C8/16 ,  G11C11/418 ,  G11C11/565

Abstract: Multi-level cell (MLC) static random access memory (SRAM) (MLC SRAM) cells configured to perform multiplication operations are disclosed. In one aspect, an MLC SRAM cell includes SRAM bit cells, wherein data values stored in SRAM bit cells correspond to a multiple-bit value stored in the MLC SRAM cell that serves as first operand in multiplication operation. Voltage applied to read bit line is applied to each SRAM bit cell, wherein the voltage is an analog representation of a multiple-bit value that serves as a second operand in the multiplication operation. For each SRAM bit cell, if a particular binary data value is stored, a current correlating to the voltage of the read bit line is added to a current sum line. A magnitude of current on the current sum line is an analog representation of a multiple-bit product of the first operand multiplied by the second operand.

公开(公告)号：US20190019564A1

公开(公告)日：2019-01-17

申请号：US15817474

申请日：2017-11-20

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Wei-Chuan Chen

IPC: G11C16/34 ,  G11C14/00 ,  G11C11/56 ,  G11C16/04 ,  H01L27/108 ,  H01L29/792 ,  H01L45/00

Abstract: Multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuits for performing matrix computations with multi-bit input vectors are disclosed. An MLC NVM matrix circuit includes a plurality of NVM storage string circuits that each include a plurality of MLC NVM storage circuits each containing a plurality of NVM bit cell circuits each configured to store 1-bit memory state. Thus, each MLC NVM storage circuit stores a multi-bit memory state according to memory states of its respective NVM bit cell circuits. Each NVM bit cell circuit includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector. Activation of the gate node of a given NVM bit cell circuit in an MLC NVM storage circuit controls whether its resistance is contributed to total resistance of an MLC NVM storage circuit coupled to a respective source line.

公开(公告)号：US09721634B2

公开(公告)日：2017-08-01

申请号：US14860931

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Yu Lu ,  Chando Park ,  Seung Hyuk Kang

IPC: G11C11/16 ,  H01L27/22

CPC classification number: G11C11/1659 ,  G11C11/02 ,  G11C11/161 ,  H01L27/228

Abstract: Magnetic tunnel junction (MTJ) memory bit cells that decouple source line layout from access transistor node size to facilitate reduced contact resistance are disclosed. In one example, an MTJ memory bit cell is provided that includes a source plate disposed above and in contact with a source contact for a source node of an access transistor. A source line is disposed above and in electrical contact with the source plate to electrically connect the source line to the source node. The source plate allows the source line to be provided in a higher metal level from the source and drain contacts of the access transistor such that the source line is not in physical contact with (i.e., decoupled from) the source contact. This allows pitch between the source line and drain column to be relaxed from the width of the source and drain nodes without having to increase contact resistance.

公开(公告)号：US09666259B1

公开(公告)日：2017-05-30

申请号：US15097166

申请日：2016-04-12

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook Jung ,  Taehui Na ,  Byung Kyu Song ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/062 ,  G11C7/065 ,  G11C11/1675

Abstract: A method of sensing a data value stored at a memory cell according to a dual mode sensing scheme includes determining, at a sensing circuit, whether a resistance of a magnetic tunnel junction (MTJ) element is within a first range of resistance values, within a second range of resistance values, or within a third range of resistance values. The MTJ element is included in the memory cell. The method also includes determining the data value stored at the memory cell according to a first mode of operation if the resistance of the MTJ element is within the first range of resistance values or within the third range of resistance values. The method further includes determining the data value stored at the memory cell according to a second mode of operation if the resistance of the MTJ element is within the second range of resistance values.

公开(公告)号：US09595666B2

公开(公告)日：2017-03-14

申请号：US15173567

申请日：2016-06-03

Applicant: QUALCOMM INCORPORATED

Inventor： Matthias Georg Gottwald ,  Jimmy Kan ,  Kangho Lee ,  Chando Park ,  Seung Hyuk Kang

IPC: H01L21/3213 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L43/10 ,  H01L27/22

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L27/222 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10

Abstract: A method for fabricating a perpendicular magnetic tunnel junction (pMTJ) device includes growing a seed layer on a first electrode of the pMTJ device. The seed layer has a uniform predetermined crystal orientation along a growth axis. The method also includes planarizing the seed layer while maintaining the uniform predetermined crystal orientation of the seed layer.

Abstract translation: 用于制造垂直磁性隧道结（pMTJ）器件的方法包括在pMTJ器件的第一电极上生长晶种层。 种子层沿生长轴具有均匀的预定晶体取向。 该方法还包括平面化种子层，同时保持种子层的均匀的预定晶体取向。

公开(公告)号：US20170059669A1

公开(公告)日：2017-03-02

申请号：US14836860

申请日：2015-08-26

Applicant: QUALCOMM Incorporated

Inventor： Jimmy Kan ,  Matthias Georg Gottwald ,  Chando Park ,  Seung Hyuk Kang

IPC: G01R33/12 ,  G11C11/16 ,  G11C29/04

CPC classification number: G01R33/1207 ,  G11C11/16 ,  G11C29/006 ,  G11C29/04 ,  G11C29/56016 ,  G11C2029/1206 ,  G11C2029/5002 ,  G11C2029/5602

Abstract: A method and apparatus for testing a magnetic memory device is provided. The method begins when a magnetic field enhancing backing plate is installed in the test fixture. The magnetic field enhancing backing plate may be installed in the wafer chuck of a wafer testing probe station. The magnetic memory device is installed in the test fixture and a magnetic field is applied to the magnetic memory device. The magnetic field may be applied in-plane or perpendicular to the magnetic memory device. The performance of the magnetic memory device may be determined based on the magnetic field applied to the device. The apparatus includes a magnetic field enhancing backing plate adapted to fit a test fixture, possibly in the wafer chuck. The magnetic field enhancing backing plate is fabricated of high permeability magnetic materials, such as low carbon steel, with a thickness based on the magnetic field used in testing.

Abstract translation: 提供一种用于测试磁存储器件的方法和装置。 当将磁场增强背板安装在测试夹具中时，该方法开始。 磁场增强背板可以安装在晶片测试探针台的晶片卡盘中。 磁存储器件安装在测试夹具中，磁场被施加到磁存储器件。 磁场可以面向或垂直于磁存储器件施加。 磁存储器件的性能可以基于施加到器件的磁场来确定。 该装置包括适于装配测试夹具（可能在晶片卡盘中）的磁场增强背板。 磁场增强背板由高磁导率磁性材料（如低碳钢）制成，厚度基于测试中使用的磁场。