公开(公告)号：US10431734B2

公开(公告)日：2019-10-01

申请号：US15467803

申请日：2017-03-23

Applicant: QUALCOMM Incorporated

Inventor： Chando Park ,  Jimmy Jianan Kan ,  Peiyuan Wang ,  Seung Hyuk Kang

IPC: H01L27/22 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08 ,  H01F10/32

Abstract: A perpendicular magnetic tunnel junction may include a free layer, a reference layer, and a barrier layer. The barrier layer may be arranged between the free layer and the reference layer. The barrier layer may include a first interface and a second interface. The first interface may face the free layer, and a second interface may face the reference layer. The first interface may not physically correlate with the second interface.

公开(公告)号：US10311930B1

公开(公告)日：2019-06-04

申请号：US15946209

申请日：2018-04-05

Applicant: QUALCOMM Incorporated

Inventor： Sungryul Kim ,  Chando Park ,  Seung Hyuk Kang

IPC: G06F7/58 ,  G11C11/16 ,  G11C17/02 ,  H04L9/32

Abstract: One-time programming (OTP) magneto-resistive random access memory (MRAM) bit cells in a physically unclonable function (PUF) memory in breakdown to a memory state from a previous read operation to provide PUF operations is disclosed. PUF memory is configured to permanently one-time program an initial randomly generated PUF output from PUF MRAM bit cells accessed in an initial PUF read operation, to the same PUF MRAM bit cells accessed in the initial PUF read operation. In this manner, the initial PUF output is randomly generated due to process variations of the PUF MRAM bit cells to maintain an initial unpredictable memory state, but the PUF output will be reproduced for subsequent PUF read operations to the same PUF MRAM bit cells in the PUF memory array for reproducibility. The OTP of the PUF MRAM bit cells can be accomplished by applying breakdown voltage to the PUF MRAM bit cells during programming.

公开(公告)号：US20180040668A1

公开(公告)日：2018-02-08

申请号：US15241595

申请日：2016-08-19

Applicant: QUALCOMM Incorporated

Inventor： Chando Park ,  Jimmy Jianan Kan ,  Seung Hyuk Kang

IPC: H01L27/22 ,  H01L43/10 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L27/228 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Aspects disclosed include reducing or avoiding metal deposition from etching magnetic tunnel junction (MTJ) devices. In one example, a width of a bottom electrode of an MTJ device is provided to be less than a width of the MTJ stack of the MTJ device. In this manner, etching of the bottom electrode may be reduced or avoided to reduce or avoid metal redeposition as a result of over-etching the MTJ device to avoid horizontal shorts between an adjacent device(s). In another example, a seed layer is embedded in a bottom electrode of the MTJ device. In this manner, the MTJ stack is reduced in height to reduce or avoid metal redeposition as a result of over-etching the MTJ device. In another example, an MTJ device includes an embedded seed layer in a bottom electrode which also has a width less than a width of the MTJ stack.

公开(公告)号：US09824735B1

公开(公告)日：2017-11-21

申请号：US15237078

申请日：2016-08-15

Applicant: QUALCOMM Incorporated

Inventor： Jimmy Jianan Kan ,  Chando Park ,  Peiyuan Wang ,  Seung Hyuk Kang

IPC: G11C11/00 ,  G11C11/16 ,  G06F7/58

CPC classification number: G11C11/161 ,  G06F7/588 ,  G11C7/24 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/1695 ,  G11C11/1697 ,  G11C11/18

Abstract: An apparatus includes a perpendicular magnetic tunnel junction (MTJ) including a free layer. The apparatus includes a spin orbit torque metal layer coupled to the perpendicular MTJ and configured to change a magnetization state of the free layer responsive to flow of a current along the spin orbit torque metal layer. The apparatus includes a random number generator configured to generate a random number at least partially based on a state of the perpendicular MTJ.

公开(公告)号：US09666792B2

公开(公告)日：2017-05-30

申请号：US14824507

申请日：2015-08-12

Applicant: QUALCOMM Incorporated

Inventor： Wei-Chuan Chen ,  Yu Lu ,  Chando Park ,  Seung Hyuk Kang

IPC: H01L21/02 ,  H01L43/12 ,  H01L43/08 ,  H01L27/22 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: Shadow-effect compensated fabrication of magnetic tunnel junction (MTJ) semiconductor elements is disclosed. Providing shadow-effect compensated fabrication of MTJ elements can provide reduced free layer sizing for enhanced MTJ operational margin. In certain aspects, to reduce size of a free layer during fabrication of an MTJ to provide enhanced write and retention symmetry, ion beam etching (IBE) fabrication process is employed to fabricate a free layer smaller than the pinned layer. To avoid asymmetrical footing being fabricated in free layer due to shadow-effect of neighboring MTJs, an ion beam directed at the MTJ is shadow-effect compensated. The angle of incidence of the ion beam directed at the MTJ is varied as the MTJ is rotated to be less steep when another MTJ is in directional line of the ion beam and the MTJ being fabricated. Thus, the free layer is etched more uniformly in the MTJ while avoiding increased etching damage.

公开(公告)号：US09614147B2

公开(公告)日：2017-04-04

申请号：US15169603

申请日：2016-05-31

Applicant: QUALCOMM Incorporated

Inventor： Chando Park ,  Kangho Lee ,  Seung Hyuk Kang

IPC: H01L43/10 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device includes a free layer. The MTJ also includes a barrier layer coupled to the free layer. The MTJ also has a fixed layer, coupled to the barrier layer. The fixed layer includes a first synthetic antiferromagnetic (SAF) multilayer having a first perpendicular magnetic anisotropy (PMA) and a first damping constant. The fixed layer also includes a second SAF multilayer having a second perpendicular magnetic anisotropy (PMA) and a second damping constant lower than the first damping constant. The first SAF multilayer is closer to the barrier layer than the second SAF multilayer. The fixed layer also includes a SAF coupling layer between the first and the second SAF multilayers.

公开(公告)号：US20170077387A1

公开(公告)日：2017-03-16

申请号：US14856372

申请日：2015-09-16

Applicant: QUALCOMM Incorporated

Inventor： Jimmy Jianan Kan ,  Matthias Georg Gottwald ,  Xiaochun Zhu ,  Chando Park ,  Seung Hyuk Kang

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L43/12 ,  H01F10/3263 ,  H01F10/3286 ,  H01F41/307 ,  H01L43/08

Abstract: Magnetic Tunnel Junction (MTJ) devices particularly suited for efficient spin-torque-transfer (STT) magnetic random access memory (MRAM) (STT MRAM) are disclosed. In one aspect, a MTJ structure with a reduced thickness first pinned layer provided below a tunnel magneto-resistance (TMR) barrier layer is provided. The first pinned layer provided below the TMR bather layer includes one pinned layer magnetized in only one magnetic orientation. In another aspect, a second pinned layer and a spacer layer are provided above a free layer and the TMR barrier layer in the MTJ. The second pinned layer is magnetized in a magnetic orientation that is anti-parallel to that of the first pinned layer. In yet another aspect, a giant magneto-resistance (GMR) spacer layer is provided as the spacer layer between the second pinned layer and the free layer in the MTJ.

Abstract translation: 公开了特别适用于高效自旋转矩传递（STT）磁随机存取存储器（MRAM）（STT MRAM）的磁隧道结（MTJ）装置。 在一个方面，提供了一种在隧道磁阻（TMR）阻挡层下方提供具有减小厚度的第一固定层的MTJ结构。 在TMR沐浴层下面提供的第一被钉扎层包括仅以一个磁性取向磁化的一个钉扎层。 在另一方面，第二被钉扎层和间隔层设置在自由层上方和MTJ中的TMR阻挡层之上。 第二被钉扎层被磁化成与第一被钉扎层反平行的磁取向。 在另一方面，提供巨磁电阻（GMR）间隔层作为MTJ中的第二被钉扎层和自由层之间的间隔层。

公开(公告)号：US20190304527A1

公开(公告)日：2019-10-03

申请号：US15939923

申请日：2018-03-29

Applicant: QUALCOMM Incorporated

Inventor： Sungryul Kim ,  Chando Park ,  Seung Hyuk Kang

IPC: G11C11/16 ,  H04L9/32 ,  H01L43/08 ,  H01L27/22

Abstract: Magneto-resistive random access memory (MRAM) employing an integrated physically unclonable function (PUF) memory. The MRAM includes an MRAM array comprising an MRAM data array of data MRAM bit cells and an MRAM PUF array comprising PUF MRAM bit cells to form an integrated MRAM PUF array in the MRAM array. A resistance sensed from the PUF MRAM bit cells is compared to a reference resistance between the reference MRAM bit cells in the accessed MRAM bit cell row circuit in response to a read operation to cancel or mitigate the effect of process variations on MRAM bit cell resistance. The difference in sensed resistance and reference resistance is used to generate a random PUF output. By integrating the MRAM PUF array into an MRAM array containing an MRAM data array, access circuitry can be shared to control access to the MRAM data array and MRAM PUF, thus saving memory area.

公开(公告)号：US10103319B2

公开(公告)日：2018-10-16

申请号：US15458641

申请日：2017-03-14

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Jimmy Kan ,  Xiaochun Zhu ,  Matthias Georg Gottwald ,  Chando Park ,  Seung Hyuk Kang

IPC: H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  H01F10/32

Abstract: A material stack of a synthetic anti-ferromagnetic (SAF) reference layer of a perpendicular magnetic tunnel junction (MTJ) may include an SAF coupling layer. The material stack may also include and an amorphous spacer layer on the SAF coupling layer. The amorphous spacer layer may include an alloy or multilayer of tantalum and cobalt or tantalum and iron or cobalt and iron and tantalum. The amorphous spacer layer may also include a treated surface of the SAF coupling layer.

公开(公告)号：US10096649B2

公开(公告)日：2018-10-09

申请号：US15241595

申请日：2016-08-19

Applicant: QUALCOMM Incorporated

Inventor： Chando Park ,  Jimmy Jianan Kan ,  Seung Hyuk Kang

IPC: H01L27/22 ,  H01L43/10 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16

Abstract: Aspects disclosed include reducing or avoiding metal deposition from etching magnetic tunnel junction (MTJ) devices. In one example, a width of a bottom electrode of an MTJ device is provided to be less than a width of the MTJ stack of the MTJ device. In this manner, etching of the bottom electrode may be reduced or avoided to reduce or avoid metal redeposition as a result of over-etching the MTJ device to avoid horizontal shorts between an adjacent device(s). In another example, a seed layer is embedded in a bottom electrode of the MTJ device. In this manner, the MTJ stack is reduced in height to reduce or avoid metal redeposition as a result of over-etching the MTJ device. In another example, an MTJ device includes an embedded seed layer in a bottom electrode which also has a width less than a width of the MTJ stack.