公开(公告)号：US20190027435A1

公开(公告)日：2019-01-24

申请号：US16144127

申请日：2018-09-27

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Kambiz Samadi ,  Jing Xie ,  Yang Du

IPC: H01L23/528 ,  H01L25/00 ,  H01L23/522 ,  H01L27/06 ,  H01L23/48 ,  H01L25/065

Abstract: Power distribution networks in a three-dimensional (3D) integrated circuit (IC) (3DIC) are disclosed. In one aspect, a voltage drop within a power distribution network in a 3DIC is reduced to reduce unnecessary power dissipation. In a first aspect, interconnect layers devoted to distribution of power within a given tier of the 3DIC are provided with an increased thickness such that a resistance of such interconnect layers is reduced relative to previously used interconnect layers and also reduced relative to other interconnect layers. Further voltage drop reductions may also be realized by placement of vias used to interconnect different tiers, and particularly, those vias used to interconnect the thickened interconnect layers devoted to the distribution of power. That is, the number, position, and/or arrangement of the vias may be controlled in the 3DIC to reduce the voltage drop.

公开(公告)号：US09041448B2

公开(公告)日：2015-05-26

申请号：US13784915

申请日：2013-03-05

Applicant: QUALCOMM Incorporated

Inventor： Yang Du ,  Jing Xie ,  Kambiz Samadi

IPC: H03K3/289 ,  H01L25/065 ,  H01L25/00 ,  H01L27/06 ,  H03K3/037

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2924/0002 ,  H03K3/0372 ,  H01L2924/00

Abstract: Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is provided to clock paths by selectively controllable flip-flops to help provide synchronous operation. In certain embodiments, 3D flip-flop are provided that include a master latch disposed in a first tier of a 3DIC. The master latch is configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output. The 3D flip-flop also includes at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output. The 3D flip-flop also includes at least one monolithic intertier via (MIV) coupling the master latch output to an input of the slave latch.

Abstract translation: 公开了一种单片三维（3D）集成电路（IC）（3DIC）和相关方法中的触发器。 在一个实施例中，为3DIC提供单个时钟源并且分配给3DIC内的元件。 通过选择性可控制的触发器提供延迟到时钟路径，以帮助提供同步操作。 在某些实施例中，提供了3D触发器，其包括设置在3DIC的第一层中的主锁存器。 主锁存器被配置为接收触发器输入和时钟输入，主锁存器被配置为提供主锁存器输出。 3D触发器还包括设置在3DIC的至少一个附加层中的至少一个从锁存器，所述至少一个从锁存器被配置为提供3DIC触发器输出。 3D触发器还包括将主锁存器输出耦合到从锁存器的输入端（MIV）的至少一个单片间隔器。

公开(公告)号：US20140269022A1

公开(公告)日：2014-09-18

申请号：US13939274

申请日：2013-07-11

Applicant: QUALCOMM Incorporated

Inventor： Jing Xie ,  Yang Du

IPC: G11C11/412

CPC classification number: G11C11/412 ,  G11C5/025 ,  G11C11/419 ,  H01L21/768 ,  H01L23/481 ,  H01L23/5226 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) (3DIC) tiers is disclosed. Related 3DICs, 3DIC processor cores, and methods are also disclosed. In embodiments disclosed herein, memory read access ports of a memory block are separated from a memory cell in different tiers of a 3DIC. 3DICs achieve higher device packing density, lower interconnect delays, and lower costs. In this manner, different supply voltages can be provided for the read access ports and the memory cell to be able to lower supply voltage for the read access ports. Static noise margins and read/write noise margins in the memory cell may be provided as a result. Providing multiple power supply rails inside a non-separated memory block that increases area can also be avoided.

Abstract translation: 公开了3D集成电路（IC）（3DIC）层中的三维（3D）存储单元分离。 还公开了相关3DIC，3DIC处理器核心和方法。 在本文公开的实施例中，存储器块的存储器读取访问端口与3DIC的不同层级的存储器单元分离。 3DIC实现更高的器件封装密度，更低的互连延迟和更低的成本。 以这种方式，可以为读访问端口和存储单元提供不同的电源电压，以便能够降低读访问端口的电源电压。 结果可能会提供存储单元中的静态噪声容限和读/写噪声余量。 还可以避免增加面积的非分开的存储块内的多个电源轨。

公开(公告)号：US20140253196A1

公开(公告)日：2014-09-11

申请号：US13784915

申请日：2013-03-05

Applicant: QUALCOMM INCORPORATED

Inventor： Yang Du ,  Jing Xie ,  Kambiz Samadi

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2924/0002 ,  H03K3/0372 ,  H01L2924/00

Abstract: Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is provided to clock paths by selectively controllable flip-flops to help provide synchronous operation. In certain embodiments, 3D flip-flop are provided that include a master latch disposed in a first tier of a 3DIC. The master latch is configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output. The 3D flip-flop also includes at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output. The 3D flip-flop also includes at least one monolithic intertier via (MIV) coupling the master latch output to an input of the slave latch.

Abstract translation: 公开了一种单片三维（3D）集成电路（IC）（3DIC）和相关方法中的触发器。 在一个实施例中，为3DIC提供单个时钟源并且分配给3DIC内的元件。 通过选择性可控制的触发器提供延迟到时钟路径，以帮助提供同步操作。 在某些实施例中，提供了3D触发器，其包括设置在3DIC的第一层中的主锁存器。 主锁存器被配置为接收触发器输入和时钟输入，主锁存器被配置为提供主锁存器输出。 3D触发器还包括设置在3DIC的至少一个附加层中的至少一个从锁存器，所述至少一个从锁存器被配置为提供3DIC触发器输出。 3D触发器还包括将主锁存器输出耦合到从锁存器的输入端（MIV）的至少一个单片间隔器。

公开(公告)号：US10121743B2

公开(公告)日：2018-11-06

申请号：US15472614

申请日：2017-03-29

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Kambiz Samadi ,  Jing Xie ,  Yang Du

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L25/065

Abstract: Power distribution networks in a three-dimensional (3D) integrated circuit (IC) (3DIC) are disclosed. In one aspect, a voltage drop within a power distribution network in a 3DIC is reduced to reduce unnecessary power dissipation. In a first aspect, interconnect layers devoted to distribution of power within a given tier of the 3DIC are provided with an increased thickness such that a resistance of such interconnect layers is reduced relative to previously used interconnect layers and also reduced relative to other interconnect layers. Further voltage drop reductions may also be realized by placement of vias used to interconnect different tiers, and particularly, those vias used to interconnect the thickened interconnect layers devoted to the distribution of power. That is, the number, position, and/or arrangement of the vias may be controlled in the 3DIC to reduce the voltage drop.

公开(公告)号：US09922956B2

公开(公告)日：2018-03-20

申请号：US14498965

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Jeffrey Lan ,  Wenyue Zhang ,  Yang Du ,  Yong Ju Lee ,  Shiqun Gu ,  Jing Xie

IPC: H01L25/065 ,  H01L21/02 ,  H01L21/265 ,  H01L21/683 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L25/00 ,  H01L27/06 ,  H01L21/822

CPC classification number: H01L25/0657 ,  H01L21/02164 ,  H01L21/265 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/528 ,  H01L25/50 ,  H01L27/0688 ,  H01L2221/68318 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A microelectromechanical system (MEMS) bond release structure is provided for manufacturing of three-dimensional integrated circuit (3D IC) devices with two or more tiers. The MEMS bond release structure includes a MEMS sacrificial release layer which may have a pillar or post structure, or alternatively, a continuous sacrificial layer for bonding and release.

公开(公告)号：US09754923B1

公开(公告)日：2017-09-05

申请号：US15149646

申请日：2016-05-09

Applicant: QUALCOMM Incorporated

Inventor： Jing Xie ,  Kambiz Samadi ,  Pratyush Kamal ,  Yang Du ,  Javid Jaffari

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  G06F17/50 ,  H01L23/48 ,  H01L27/06

CPC classification number: H01L25/0657 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/78 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L24/13 ,  H01L25/16 ,  H01L27/0688 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/1434

Abstract: Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs) are disclosed. Exemplary aspects of the present disclosure contemplate consolidating power gating circuits or cells into a single tier within a 3DIC. Still further, the power gating circuits are consolidated in a tier closest to a voltage source. This closest tier may include a backside metal layer that allows a distance between the voltage source and the power gating circuits to be minimized. By minimizing the distance between the voltage source and the power gating circuits, power loss from routing elements therebetween is minimized. Further, by consolidating the power gating circuits in a single tier, routing distances between the power gating circuits and downstream elements may be minimized and power loss from those routing elements are minimized. Other advantages are likewise realized by placement of the power gating circuits according to exemplary aspects of the present disclosure.

公开(公告)号：US08984463B2

公开(公告)日：2015-03-17

申请号：US13792592

申请日：2013-03-11

Applicant: QUALCOMM Incorporated

Inventor： Jing Xie ,  Yang Du

IPC: G06F17/50 ,  H01L23/522 ,  G11C5/14 ,  G06F1/32

CPC classification number: G06F17/5072 ,  G06F1/32 ,  G06F1/3287 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/62 ,  G11C5/14 ,  H01L23/5226 ,  H01L2924/0002 ,  H03K19/0008 ,  H01L2924/00

Abstract: The disclosed embodiments comprise a multi-stage circuit operating across different power domains. The multi-stage circuit may be implemented as a master-slave flip-flop circuit integrated with a level shifter that transfers data across different power domains. The master and slave stages of the flip-flop may be split across two tiers of a 3D IC and may include (i) a level shifter across different power domain integrated within the flip-flop circuit, (ii) reduced one-state writing delays by a self-induced power collapsing technique, (iii) splitting flip-flop power supplies in different tiers using monolithic 3D IC technology, and (iv) cross power domain data transfer between 3D IC tiers.

Abstract translation: 所公开的实施例包括跨越不同功率域操作的多级电路。 多级电路可以实现为与电平转换器集成的主从触发器电路，其在不同的电源域之间传送数据。 触发器的主级和从属级可以分为三层3D IC的两层，并且可以包括（i）跨越触发器电路中的不同功率域的电平移位器，（ii）减少的一状态写入延迟 通过自感电源塌陷技术，（iii）使用单片3D IC技术分割不同层级的触发器电源，以及（iv）3D IC层之间的跨功率域数据传输。

公开(公告)号：US09929733B1

公开(公告)日：2018-03-27

申请号：US15437871

申请日：2017-02-21

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Kambiz Samadi ,  Jing Xie ,  Yang Du

IPC: H01L23/522 ,  H03K19/094 ,  H01L23/528 ,  H01L27/06 ,  H01L27/118

CPC classification number: H03K19/094 ,  G06F17/505 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/11807 ,  H01L2027/11851 ,  H01L2027/11872 ,  H01L2027/11875

Abstract: A 3D integrated circuit reduces delay when a signal traverses logical blocks of the integrated circuit. In one instance, the 3D integrated circuit has a first tier and a second tier including one or more first and second logical blocks, respectively. The first logical block(s) include a first primary output logic gate, a first primary input logic gate, a first primary input pin and a first primary output pin. The first primary output pin lies within a perimeter defined by a total area occupied by logic gates of the first logical block(s). The second logical block(s) include a second primary output logic gate, a second primary input logic gate, a second primary input pin and a second primary output pin. The second primary input pin is coupled to the first primary output pin.

公开(公告)号：US09171608B2

公开(公告)日：2015-10-27

申请号：US13939274

申请日：2013-07-11

Applicant: QUALCOMM Incorporated

Inventor： Jing Xie ,  Yang Du

IPC: G11C5/06 ,  G11C11/412 ,  G11C5/02 ,  H01L27/06 ,  H01L27/11

CPC classification number: G11C11/412 ,  G11C5/025 ,  G11C11/419 ,  H01L21/768 ,  H01L23/481 ,  H01L23/5226 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) (3DIC) tiers is disclosed. Related 3DICs, 3DIC processor cores, and methods are also disclosed. In embodiments disclosed herein, memory read access ports of a memory block are separated from a memory cell in different tiers of a 3DIC. 3DICs achieve higher device packing density, lower interconnect delays, and lower costs. In this manner, different supply voltages can be provided for the read access ports and the memory cell to be able to lower supply voltage for the read access ports. Static noise margins and read/write noise margins in the memory cell may be provided as a result. Providing multiple power supply rails inside a non-separated memory block that increases area can also be avoided.

Abstract translation: 公开了3D集成电路（IC）（3DIC）层中的三维（3D）存储单元分离。 还公开了相关3DIC，3DIC处理器核心和方法。 在本文公开的实施例中，存储器块的存储器读取访问端口与3DIC的不同层级的存储器单元分离。 3DIC实现更高的器件封装密度，更低的互连延迟和更低的成本。 以这种方式，可以为读访问端口和存储单元提供不同的电源电压，以便能够降低读访问端口的电源电压。 结果可能会提供存储单元中的静态噪声容限和读/写噪声余量。 还可以避免增加面积的非分开的存储块内的多个电源轨。