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    Molecular wire crossbar memory
    1.
    发明授权
    Molecular wire crossbar memory 有权
    分子线交叉记忆

    公开(公告)号：US6128214A

    公开(公告)日：2000-10-03

    申请号：US280189

    申请日：1999-03-29

    申请人： Philip J. Kuekes ,  R. Stanley Williams ,  James R. Heath

    发明人： Philip J. Kuekes ,  R. Stanley Williams ,  James R. Heath

    IPC分类号： G11C11/14 ,  G11C11/36 ,  G11C13/02 ,  H01L27/28 ,  H01L51/00 ,  G11C11/00

    CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C11/14 ,  G11C13/0009 ,  G11C2213/77 ,  G11C2213/81 ,  H01L27/28 ,  H01L51/0595 ,  Y10S977/943

    摘要： A molecular wire crossbar memory (MWCM) system is provided. The MWCM comprises a two-dimensional array of a plurality of nanometer-scale devices, each device comprising a junction formed by a pair of crossed wires where one wire crosses another and at least one connector species connecting the pair of crossed wires in the junction. The connector species comprises a bi-stable molecular switch. The junction forms either a resistor or a diode or an asymmetric non-linear resistor. The junction has a state that is capable of being altered by application of a first voltage and sensed by application of a second, non-destructive voltage.

    摘要翻译： 提供分子线交叉存储器（MWCM）系统。 MWCM包括多个纳米级装置的二维阵列，每个装置包括由一对交叉导线形成的连接点，其中一根线交叉另一条线和连接该交叉线中的该对交叉线的至少一个连接器种类。 连接器种类包括双稳态分子开关。 该结形成电阻器或二极管或非对称非线性电阻器。 连接点具有能够通过施加第一电压并被施加第二非破坏性电压而被改变的状态。

    Chemically synthesized and assembled electronics devices
    4.
    发明授权
    Chemically synthesized and assembled electronics devices 失效
    化学合成和组装的电子器件

    公开(公告)号：US06459095B1

    公开(公告)日：2002-10-01

    申请号：US09282048

    申请日：1999-03-29

    申请人： James R. Heath ,  R. Stanley Williams ,  Philip J. Kuekes

    发明人： James R. Heath ,  R. Stanley Williams ,  Philip J. Kuekes

    IPC分类号： H01L2906

    CPC分类号： H01L27/10 ,  B82B1/00 ,  B82Y10/00 ,  B82Y30/00 ,  G11C13/0009 ,  G11C13/0014 ,  G11C13/02 ,  G11C2213/72 ,  G11C2213/77 ,  G11C2213/81 ,  H01L51/0595 ,  Y10S977/704 ,  Y10S977/705 ,  Y10S977/936

    摘要： A route to the fabrication of electronic devices is provided, in which the devices consist of two crossed wires sandwiching an electrically addressable molecular species. The approach is extremely simple and inexpensive to implement, and scales from wire dimensions of several micrometers down to nanometer-scale dimensions. The device of the present invention can be used to produce crossbar switch arrays, logic devices, memory devices, and communication and signal routing devices. The present invention enables construction of molecular electronic devices on a length scale than can range from micrometers to nanometers via a straightforward and inexpensive chemical assembly procedure. The device is either partially or completely chemically assembled, and the key to the scaling is that the location of the devices on the substrate are defined once the devices have been assembled, not prior to assembly.

    摘要翻译： 提供了制造电子器件的途径，其中器件由夹着电可寻址分子种类的两条交叉导线组成。 该方法实现起来非常简单和便宜，并且从几微米的线尺寸缩小到纳米级尺寸。 本发明的装置可用于产生交叉开关阵列，逻辑器件，存储器件以及通信和信号路由器件。 本发明能够通过直接且廉价的化学组装程序在比例范围从微米到纳米的范围内构建分子电子器件。 该装置部分或完全化学地组装，并且缩放的关键在于，一旦装置组装而不是装配之前，基板上的装置的位置被定义。

    Molecular-wire crossbar interconnect (MWCI) for signal routing and communications
    5.
    发明授权
    Molecular-wire crossbar interconnect (MWCI) for signal routing and communications 失效
    用于信号路由和通信的分子线交叉互连（MWCI）

    公开(公告)号：US06314019B1

    公开(公告)日：2001-11-06

    申请号：US09280225

    申请日：1999-03-29

    申请人： Philip J. Kuekes ,  R. Stanley Williams ,  James R. Heath

    发明人： Philip J. Kuekes ,  R. Stanley Williams ,  James R. Heath

    IPC分类号： G11C1100

    CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C13/0009 ,  G11C2213/34 ,  G11C2213/77 ,  G11C2213/81 ,  Y10S977/708 ,  Y10S977/762 ,  Y10S977/765 ,  Y10S977/936

    摘要： A molecular-wire crossbar interconnect for signal routing and communications between a first level and a second level in a molecular-wire crossbar is provided. The molecular wire crossbar comprises a two-dimensional array of a plurality of nanometer-scale switches. Each switch is reconfigurable and self-assembling and comprises a pair of crossed wires which form a junction where one wire crosses another and at least one connector species connecting the pair of crossed wires in the junction. The connector species comprises a bi-stable molecule. Each level comprises at least one group of switches and each group of switches comprises at least one switch, with each group in the first level connected to all other groups in the second level in an all-to-all configuration to provide a scalable, defect-tolerant, fat-tree networking scheme. The primary advantage is ease of fabrication, because an active switch is formed any time two wires cross. This saves tremendously on circuit area (a factor of a few times ten), since no other wires or ancillary devices are needed to operate the switch or store the required configuration. This reduction of the area of a configuration bit and its switch to just the area of two crossing wires is a major advantage in constructing a defect-tolerant interconnect network.

    摘要翻译： 提供了用于分子线交叉开关中的信号路由和第一级和第二级之间的通信的分子线交叉开关互连。 分子线交叉杆包括多个纳米级开关的二维阵列。 每个开关是可重构和自组装的，并且包括一对交叉线，其形成一条线与另一条线交叉的连接处，以及至少一个在连接处连接一对交叉线的连接器种类。 连接器种类包括双稳态分子。 每个级别包括至少一组交换机，并且每组交换机包括至少一个交换机，其中第一级别中的每个组以全对齐配置连接到第二级别中的所有其他组，以提供可扩展的缺陷 不容忍，胖树联网方案。 主要优点是易于制造，因为在任何时候两根线交叉时形成有源开关。 由于不需要其他电线或辅助设备来操作交换机或存储所需的配置，因此可大大节省电路面积（十倍）。 配置位区域的这种减少及其切换到两条交叉电线的区域是构建容错互连网络的主要优点。

    Switching device and methods for controlling electron tunneling therein
    6.
    发明授权
    Switching device and methods for controlling electron tunneling therein 有权
    用于控制电子隧穿的开关装置和方法

    公开(公告)号：US08502198B2

    公开(公告)日：2013-08-06

    申请号：US11414578

    申请日：2006-04-28

    申请人： R. Stanley Williams ,  Zhiyong Li ,  Douglas Ohlberg ,  Philip J. Kuekes ,  Duncan Stewart

    发明人： R. Stanley Williams ,  Zhiyong Li ,  Douglas Ohlberg ,  Philip J. Kuekes ,  Duncan Stewart

    IPC分类号： H01L29/08

    CPC分类号： G11C13/02 ,  G11C13/0009 ,  G11C2213/77 ,  H01L51/0591

    摘要： A switching device includes at least one bottom electrode and at least one top electrode. The top electrode crosses the bottom electrode at a non-zero angle, thereby forming a junction. A metal oxide layer is established on at least one of the bottom electrode or the top electrode. A molecular layer including a monolayer of organic molecules and a source of water molecules is established in the junction. Upon introduction of a forward bias, the molecular layer facilitates a redox reaction between the electrodes, thereby reducing a tunneling gap between the electrodes.

    摘要翻译： 开关装置包括至少一个底部电极和至少一个顶部电极。 顶部电极以非零角度穿过底部电极，从而形成结。 在底电极或顶电极中的至少一个上建立金属氧化物层。 在连接处建立了包括有机分子单层和水分子源的分子层。 在引入正向偏压时，分子层促进电极之间的氧化还原反应，从而减少电极之间的隧道间隙。

    Scalable, component-accessible, and highly interconnected three-dimensional component arrangement within a system
    7.
    发明授权
    Scalable, component-accessible, and highly interconnected three-dimensional component arrangement within a system 有权
    系统内可扩展的，可组件访问的和高度互连的三维组件布置

    公开(公告)号：US08214786B2

    公开(公告)日：2012-07-03

    申请号：US10935845

    申请日：2004-09-08

    申请人： Philip J. Kuekes ,  R. Stanley Williams ,  Raymond G. Beausoleil, Jr.

    发明人： Philip J. Kuekes ,  R. Stanley Williams ,  Raymond G. Beausoleil, Jr.

    IPC分类号： G06F17/50

    CPC分类号： G06F1/18 ,  G06F17/509 ,  H05K7/1444

    摘要： Embodiments of the present invention include dense, but accessible and well-interconnected component arrangements within multi-component systems, such as high-end multi-processor computer systems, and methods for constructing such arrangements. In a described embodiment, integrated-circuit-containing processing components, referred to as a “flat components,” are arranged into local blocks of intercommunicating flat components. The local flat-component blocks are arranged into interconnected, primitive multi-local-block repeating units, and the primitive local-block repeating units are layered together in a three-dimensional, regularly repeating structure that can be assembled to approximately fill any specified three-dimensional volume. The arrangement provides for relatively short, direct pathways from the surface of the specified volume to any particular local block and flat component within the three-dimensional arrangement.

    摘要翻译： 本发明的实施例包括在诸如高端多处理器计算机系统的多组件系统内的密集但可访问和良好互连的组件布置，以及用于构造这种布置的方法。 在所描述的实施例中，被称为“平面部件”的集成电路的处理部件被布置在相互连通的平面部件的局部块中。 本地平面组件块被布置成互连的原始多局部块重复单元，并且原始局部块重复单元以三维的规则重复的结构分层在一起，其可以被组装以大致填充任何指定的三 维数。 该装置提供从指定体积的表面到三维布置中的任何特定局部块和平坦部件的相对短的直接通路。

    Defect-and-failure-tolerant demultiplexer using series replication and error-control encoding
    8.
    发明授权
    Defect-and-failure-tolerant demultiplexer using series replication and error-control encoding 有权
    使用序列复制和错误控制编码的缺陷和容错解复用器

    公开(公告)号：US07872502B2

    公开(公告)日：2011-01-18

    申请号：US11484961

    申请日：2006-07-12

    申请人： Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

    发明人： Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

    IPC分类号： H03K19/094

    CPC分类号： H03K19/007 ,  G06F11/1076 ,  H03K19/00315

    摘要： One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, each including a reversibly switchable interconnection between a number of address lines, or address-line-derived signal lines, and an output signal line. Each reversibly switchable interconnection includes one or more reversibly switchable elements. In certain demultiplexer embodiments, NMOS and/or PMOS transistors are employed as reversibly switchable elements. In the method that represents one embodiment of the present invention, two or more serially connected transistors are employed in each reversibly switchable interconnection, so that short defects in up to one less than the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection. In addition, error-control-encoding techniques are used to introduce additional address-line-derived signal lines and additional switchable interconnections so that the demultiplexer may function even when a number of individual, switchable interconnections are open-defective.

    摘要翻译： 本发明的一个实施例是一种用于构建缺陷和容错解复用器的方法。 该方法适用于纳米尺度，微米级或更大规模的解复用器电路。 解复用器电路可以被视为一组与门，每个与门包括多个地址线或地址线导出的信号线之间的可逆切换互连以及输出信号线。 每个可逆切换互连包括一个或多个可逆切换元件。 在某些解复用器实施例中，NMOS和/或PMOS晶体管被用作可逆切换元件。 在表示本发明的一个实施例的方法中，在每个可逆切换互连中使用两个或更多个串联连接的晶体管，使得比串联互连晶体管的数量少一个的短缺陷不会导致可逆地失效 可切换互连。 此外，误差控制编码技术用于引入附加的地址线导出的信号线和附加的可切换互连，使得即使当多个单独的可切换互连是开放缺陷时，解复用器也可以起作用。

    Nanoscale interconnection interface
    9.
    发明申请
    Nanoscale interconnection interface 有权
    纳米级互连接口

    公开(公告)号：US20100293518A1

    公开(公告)日：2010-11-18

    申请号：US12011175

    申请日：2008-01-23

    申请人： Philip J. Kuekes ,  J. Warren Robinett ,  Gadiel Seroussl ,  R. Stanley Williams

    发明人： Philip J. Kuekes ,  J. Warren Robinett ,  Gadiel Seroussl ,  R. Stanley Williams

    IPC分类号： G06F17/50

    CPC分类号： G11C13/0023 ,  B82Y10/00 ,  G06F11/1016 ,  G11C8/10 ,  G11C11/54 ,  G11C13/0002 ,  G11C2213/77 ,  G11C2213/81

    摘要： One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines to 2k or fewer nanowires, employing supplemental, internal address lines to map 2k nanowire addresses to a larger, internal, n-bit address space, where n>k. A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2k nanowires, with n>k, using 2k, well-distributed, n-bit external addresses to access the 2k nanowires. Additional embodiments of the present invention include a method for evaluating different mappings of nanowire addresses to internal address-spaces of different sizes, or to evaluate mappings of nanowires to external address-spaces of different sizes, metrics for evaluating address mapping and demultiplexer designs, and demultiplexer design methods.

    摘要翻译： 本发明的一个实施例提供了一种解复用器，其实现为纳米线交叉开关或具有电阻器状纳米线结的混合纳米线/微型信号线交叉开关。 一个实施例的解复用器提供在k个微米地址线上输入的信号到2k个或更少的纳米线的解复用，采用补充的内部地址线将2k个纳米线地址映射到更大的内部n位地址空间，其中n> k。 本发明的第二解复用器实施例使用2k，均匀分布的n位外部地址来访问2k纳米线，在n个微米级地址线上输入的信号到2k纳米线解复用n> k。 本发明的另外的实施例包括用于评估纳米线地址与不同大小的内部地址空间的不同映射的方法，或者评估纳米线与不同大小的外部地址空间的映射，用于评估地址映射和解复用器设计的度量，以及 解复用器设计方法。