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公开(公告)号：US08121807B2
公开(公告)日：2012-02-21
申请号：US12288021
申请日：2008-10-15
IPC分类号： G01R27/28
CPC分类号： G01R31/317
摘要： Embodiments of the present invention are directed to cost-effective defect amelioration in manufactured electronic devices that include nanoscale components. Certain embodiments of the present invention are directed to amelioration of defects in electronic devices that contain nanoscale demultiplexers. In certain embodiments of the present invention, the nanoscale-demultiplexer-containing devices include reconfigurable encoders. In one embodiment of the present invention, the table of codes within a reconfigurable encoder is permuted, and a device is configured in accordance with the permuted codes, in order to produce a permuted table of codes that, when input to an appropriately configured nanoscale demultiplexer, produces correct outputs despite defects in the nanoscale demultiplexer.
摘要翻译： 本发明的实施例涉及在包括纳米级组件的制造的电子设备中的经济有效的缺陷改善。 本发明的某些实施例涉及改善包含纳米级解复用器的电子设备中的缺陷。 在本发明的某些实施例中，含纳米级解复用器的装置包括可重构编码器。 在本发明的一个实施例中，可重构编码器内的代码表被置换，并且根据置换代码配置器件，以便产生置换的代码表，当输入到适当配置的纳米级解复用器 ，尽管纳米级解复用器中存在缺陷，但仍能产生正确的输出。
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公开(公告)号：US08112700B2
公开(公告)日：2012-02-07
申请号：US12011175
申请日：2008-01-23
IPC分类号： G11C29/00
CPC分类号： G11C13/0023 , B82Y10/00 , G06F11/1016 , G11C8/10 , G11C11/54 , G11C13/0002 , G11C2213/77 , G11C2213/81
摘要： One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines to 2k or fewer nanowires, employing supplemental, internal address lines to map 2k nanowire addresses to a larger, internal, n-bit address space, where n>k. A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2k nanowires, with n>k, using 2k, well-distributed, n-bit external addresses to access the 2k nanowires. Additional embodiments of the present invention include a method for evaluating different mappings of nanowire addresses to internal address-spaces of different sizes, or to evaluate mappings of nanowires to external address-spaces of different sizes, metrics for evaluating address mapping and demultiplexer designs, and demultiplexer design methods.
摘要翻译： 本发明的一个实施例提供了一种解复用器，其实现为纳米线交叉开关或具有电阻器状纳米线结的混合纳米线/微型信号线交叉开关。 一个实施例的解复用器提供在k个微米地址线上输入的信号到2k个或更少的纳米线的解复用，采用补充的内部地址线将2k个纳米线地址映射到更大的内部n位地址空间，其中n> k。 本发明的第二解复用器实施例使用2k，均匀分布的n位外部地址来访问2k纳米线，在n个微米级地址线上输入的信号到2k纳米线解复用n> k。 本发明的另外的实施例包括用于评估纳米线地址与不同大小的内部地址空间的不同映射的方法，或者评估纳米线与不同大小的外部地址空间的映射，用于评估地址映射和解复用器设计的度量，以及 解复用器设计方法。
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3.发明授权Defect-and-failure-tolerant demultiplexer using series replication and error-control encoding 有权使用序列复制和错误控制编码的缺陷和容错解复用器公开(公告)号：US07872502B2
公开(公告)日：2011-01-18
申请号：US11484961
申请日：2006-07-12
IPC分类号： H03K19/094
CPC分类号： H03K19/007 , G06F11/1076 , H03K19/00315
摘要： One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, each including a reversibly switchable interconnection between a number of address lines, or address-line-derived signal lines, and an output signal line. Each reversibly switchable interconnection includes one or more reversibly switchable elements. In certain demultiplexer embodiments, NMOS and/or PMOS transistors are employed as reversibly switchable elements. In the method that represents one embodiment of the present invention, two or more serially connected transistors are employed in each reversibly switchable interconnection, so that short defects in up to one less than the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection. In addition, error-control-encoding techniques are used to introduce additional address-line-derived signal lines and additional switchable interconnections so that the demultiplexer may function even when a number of individual, switchable interconnections are open-defective.
摘要翻译： 本发明的一个实施例是一种用于构建缺陷和容错解复用器的方法。 该方法适用于纳米尺度，微米级或更大规模的解复用器电路。 解复用器电路可以被视为一组与门，每个与门包括多个地址线或地址线导出的信号线之间的可逆切换互连以及输出信号线。 每个可逆切换互连包括一个或多个可逆切换元件。 在某些解复用器实施例中，NMOS和/或PMOS晶体管被用作可逆切换元件。 在表示本发明的一个实施例的方法中，在每个可逆切换互连中使用两个或更多个串联连接的晶体管，使得比串联互连晶体管的数量少一个的短缺陷不会导致可逆地失效 可切换互连。 此外，误差控制编码技术用于引入附加的地址线导出的信号线和附加的可切换互连，使得即使当多个单独的可切换互连是开放缺陷时，解复用器也可以起作用。
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公开(公告)号：US20100293518A1
公开(公告)日：2010-11-18
申请号：US12011175
申请日：2008-01-23
IPC分类号： G06F17/50
CPC分类号： G11C13/0023 , B82Y10/00 , G06F11/1016 , G11C8/10 , G11C11/54 , G11C13/0002 , G11C2213/77 , G11C2213/81
摘要： One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines to 2k or fewer nanowires, employing supplemental, internal address lines to map 2k nanowire addresses to a larger, internal, n-bit address space, where n>k. A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2k nanowires, with n>k, using 2k, well-distributed, n-bit external addresses to access the 2k nanowires. Additional embodiments of the present invention include a method for evaluating different mappings of nanowire addresses to internal address-spaces of different sizes, or to evaluate mappings of nanowires to external address-spaces of different sizes, metrics for evaluating address mapping and demultiplexer designs, and demultiplexer design methods.
摘要翻译： 本发明的一个实施例提供了一种解复用器，其实现为纳米线交叉开关或具有电阻器状纳米线结的混合纳米线/微型信号线交叉开关。 一个实施例的解复用器提供在k个微米地址线上输入的信号到2k个或更少的纳米线的解复用，采用补充的内部地址线将2k个纳米线地址映射到更大的内部n位地址空间，其中n> k。 本发明的第二解复用器实施例使用2k，均匀分布的n位外部地址来访问2k纳米线，在n个微米级地址线上输入的信号到2k纳米线解复用n> k。 本发明的另外的实施例包括用于评估纳米线地址与不同大小的内部地址空间的不同映射的方法，或者评估纳米线与不同大小的外部地址空间的映射，用于评估地址映射和解复用器设计的度量，以及 解复用器设计方法。
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公开(公告)号：US20100091662A1
公开(公告)日：2010-04-15
申请号：US12288035
申请日：2008-10-15
IPC分类号： H04J3/14
CPC分类号： H04J3/047 , H03K17/002 , H03K19/0021 , H03K19/003
摘要： Embodiments of the present invention include defect-tolerant demultiplexer crossbars that employ, or that can be modeled by demultiplexer crossbars that employ, threshold logic “TL” elements. The threshold-logic elements provide for tolerance for signal variation on internal signals lines of a defect-tolerant demultiplexer crossbar, and thus tolerance for defects which produce internal signal variation.
摘要翻译： 本发明的实施例包括采用阈值逻辑“TL”元素的采用或可以通过解复用器交叉开关建模的缺陷容许解复用器交叉开关。 阈值逻辑元件提供了对于容错解复用器交叉开关的内部信号线上的信号变化的容限，并因此提供产生内部信号变化的缺陷的容限。
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6.发明申请Defect-and-failure-tolerant demultiplexer using series replication and error-control encoding 有权使用系列复制和错误控制编码的缺陷和容错解复用器公开(公告)号：US20080013393A1
公开(公告)日：2008-01-17
申请号：US11484961
申请日：2006-07-12
IPC分类号： G11C17/18
CPC分类号： H03K19/007 , G06F11/1076 , H03K19/00315
摘要： One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, each including a reversibly switchable interconnection between a number of address lines, or address-line-derived signal lines, and an output signal line. Each reversibly switchable interconnection includes one or more reversibly switchable elements. In certain demultiplexer embodiments, NMOS and/or PMOS transistors are employed as reversibly switchable elements. In the method that represents one embodiment of the present invention, two or more serially connected transistors are employed in each reversibly switchable interconnection, so that short defects in up to one less than the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection. In addition, error-control-encoding techniques are used to introduce additional address-line-derived signal lines and additional switchable interconnections so that the demultiplexer may function even when a number of individual, switchable interconnections are open-defective.
摘要翻译： 本发明的一个实施例是一种用于构建缺陷和容错解复用器的方法。 该方法适用于纳米尺度，微米级或更大规模的解复用器电路。 解复用器电路可以被视为一组与门，每个与门包括多个地址线或地址线导出的信号线之间的可逆切换互连以及输出信号线。 每个可逆切换互连包括一个或多个可逆切换元件。 在某些解复用器实施例中，NMOS和/或PMOS晶体管被用作可逆切换元件。 在表示本发明的一个实施例的方法中，在每个可逆切换互连中使用两个或更多个串联连接的晶体管，使得比串联互连晶体管的数量少一个的短缺陷不会导致可逆地失效 可切换互连。 此外，误差控制编码技术用于引入附加的地址线导出的信号线和附加的可切换互连，使得即使当多个单独的可切换互连是开放缺陷时，解复用器也可以起作用。
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公开(公告)号：US20100094580A1
公开(公告)日：2010-04-15
申请号：US12288021
申请日：2008-10-15
IPC分类号： G01R31/00
CPC分类号： G01R31/317
摘要： Embodiments of the present invention are directed to cost-effective defect amelioration in manufactured electronic devices that include nanoscale components. Certain embodiments of the present invention are directed to amelioration of defects in electronic devices that contain nanoscale demultiplexers. In certain embodiments of the present invention, the nanoscale-demultiplexer-containing devices include reconfigurable encoders. In one embodiment of the present invention, the table of codes within a reconfigurable encoder is permuted, and a device is configured in accordance with the permuted codes, in order to produce a permuted table of codes that, when input to an appropriately configured nanoscale demultiplexer, produces correct outputs despite defects in the nanoscale demultiplexer.
摘要翻译： 本发明的实施例涉及在包括纳米级组件的制造的电子设备中的经济有效的缺陷改善。 本发明的某些实施例涉及改善包含纳米级解复用器的电子设备中的缺陷。 在本发明的某些实施例中，含纳米级解复用器的装置包括可重构编码器。 在本发明的一个实施例中，可重构编码器内的代码表被置换，并且根据置换代码配置器件，以便产生置换的代码表，当输入到适当配置的纳米级解复用器 ，尽管纳米级解复用器中存在缺陷，但仍能产生正确的输出。
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8.发明申请DEFECT-AND-FAILURE-TOLERANT DEMULTIPLEXER USING SERIES REPLICATION AND ERROR-CONTROL ENCODING 审中-公开使用系列复制和错误控制编码的缺陷和失败的解复用器公开(公告)号：US20110057683A1
公开(公告)日：2011-03-10
申请号：US12947585
申请日：2010-11-16
IPC分类号： H03K19/003
CPC分类号： H03K19/007 , G06F11/1076 , H03K19/00315
摘要： One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, each including a reversibly switchable interconnection between a number of address lines, or address-line-derived signal lines, and an output signal line. Each reversibly switchable interconnection includes one or more reversibly switchable elements. In certain demultiplexer embodiments, NMOS and/or PMOS transistors are employed as reversibly switchable elements. In the method that represents one embodiment of the present invention, two or more serially connected transistors are employed in each reversibly switchable interconnection, so that short defects in up to one less than the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection. In addition, error-control-encoding techniques are used to introduce additional address-line-derived signal lines and additional switchable interconnections so that the demultiplexer may function even when a number of individual, switchable interconnections are open-defective.
摘要翻译： 本发明的一个实施例是一种用于构建缺陷和容错解复用器的方法。 该方法适用于纳米尺度，微米级或更大规模的解复用器电路。 解复用器电路可以被视为一组与门，每个与门包括多个地址线或地址线导出的信号线之间的可逆切换互连以及输出信号线。 每个可逆切换互连包括一个或多个可逆切换元件。 在某些解复用器实施例中，NMOS和/或PMOS晶体管被用作可逆切换元件。 在表示本发明的一个实施例的方法中，在每个可逆切换互连中使用两个或更多个串联连接的晶体管，使得比串联互连晶体管的数量少一个的短缺陷不会导致可逆地失效 可切换互连。 此外，误差控制编码技术用于引入附加的地址线导出的信号线和附加的可切换互连，使得即使当多个单独的可切换互连是开放缺陷时，解复用器也可以起作用。
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公开(公告)号：US07899091B2
公开(公告)日：2011-03-01
申请号：US12288035
申请日：2008-10-15
IPC分类号： H04J99/00
CPC分类号： H04J3/047 , H03K17/002 , H03K19/0021 , H03K19/003
摘要： Embodiments of the present invention include defect-tolerant demultiplexer crossbars that employ, or that can be modeled by demultiplexer crossbars that employ, threshold logic “TL” elements. The threshold-logic elements provide for tolerance for signal variation on internal signals lines of a defect-tolerant demultiplexer crossbar, and thus tolerance for defects which produce internal signal variation.
摘要翻译： 本发明的实施例包括采用阈值逻辑“TL”元素的采用或可以通过解复用器交叉开关建模的缺陷容许解复用器交叉开关。 阈值逻辑元件提供了对于容错解复用器交叉开关的内部信号线上的信号变化的容限，并因此提供产生内部信号变化的缺陷的容限。
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公开(公告)号：US07350132B2
公开(公告)日：2008-03-25
申请号：US11115887
申请日：2005-04-26
IPC分类号： H03M10/00
CPC分类号： G11C13/0023 , B82Y10/00 , G06F11/1016 , G11C8/10 , G11C11/54 , G11C13/0002 , G11C2213/77 , G11C2213/81
摘要： One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines to 2k or fewer nanowires, employing supplemental, internal address lines to map 2k nanowire addresses to a larger, internal, n-bit address space, where n>k. A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2k nanowires, with n>k, using 2k, well-distributed, n-bit external addresses to access the 2k nanowires. Additional embodiments of the present invention include a method for evaluating different mappings of nanowire addresses to internal address-spaces of different sizes, or to evaluate mappings of nanowires to external address-spaces of different sizes, metrics for evaluating address mapping and demultiplexer designs, and demultiplexer design methods.
摘要翻译： 本发明的一个实施例提供了一种解复用器，其实现为纳米线交叉开关或具有电阻器状纳米线结的混合纳米线/微型信号线交叉开关。 一个实施例的解复用器提供了在k个微米地址线上输入的信号到2k或更少的纳米线的解复用，使用补充的内部地址线将2nm的纳米线地址映射到 较大的内部n位地址空间，其中n> k。 本发明的第二解复用器实施例提供了在n个微米级地址线上输入的信号，其中n≥k，使用2分布良好的二极管， n位外部地址以访问2nm的纳米线。 本发明的另外的实施例包括用于评估纳米线地址与不同大小的内部地址空间的不同映射的方法，或者评估纳米线与不同大小的外部地址空间的映射，用于评估地址映射和解复用器设计的度量，以及 解复用器设计方法。
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