公开(公告)号：US09142546B2

公开(公告)日：2015-09-22

申请号：US14098199

申请日：2013-12-05

申请人： Patrick B. Shea ,  Michael Rennie ,  Sandro J. Di Giacomo

发明人： Patrick B. Shea ,  Michael Rennie ,  Sandro J. Di Giacomo

IPC分类号： H01L21/336 ,  H01L21/331 ,  H01L21/338 ,  H01L21/337 ,  H01L21/8249 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/092 ,  H01L29/737 ,  H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L21/265

CPC分类号： H01L27/0711 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/092 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7378

摘要： A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region.

摘要翻译： 提供了形成双极晶体管器件的方法。 该方法包括在集电极有源区域上的衬底上沉积集电极电介质层，在集电极电介质层上沉积电介质抗反射（DARC）层，干蚀刻掉DARC层中的基底开口，并湿法蚀刻掉部分 的基底开口中的集电极介电层，以提供到基板的延伸的基部开口。 该方法还包括进行基底沉积以在延伸的基底开口中形成基底外延区域，并且延伸在DARC层的第一和第二部分上，该DARC层由于干蚀刻而残留在DARC层中的基底开口处，并形成 在基底外延区域上的发射极区域。

公开(公告)号：US20150357448A1

公开(公告)日：2015-12-10

申请号：US14829487

申请日：2015-08-18

申请人： PATRICK B. SHEA ,  Michael Rennie ,  Sandro J. Di Giacomo

发明人： PATRICK B. SHEA ,  Michael Rennie ,  Sandro J. Di Giacomo

IPC分类号： H01L29/737 ,  H01L29/08 ,  H01L27/07 ,  H01L29/10

CPC分类号： H01L27/0711 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/092 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7378

摘要： A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region.

公开(公告)号：US09812445B2

公开(公告)日：2017-11-07

申请号：US14829487

申请日：2015-08-18

申请人： Patrick B. Shea ,  Michael Rennie ,  Sandro J. Di Giacomo

发明人： Patrick B. Shea ,  Michael Rennie ,  Sandro J. Di Giacomo

IPC分类号： H01L27/07 ,  H01L29/10 ,  H01L29/08 ,  H01L29/737 ,  H01L29/66 ,  H01L27/06 ,  H01L21/8249

CPC分类号： H01L27/0711 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/092 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7378

摘要： A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region.

公开(公告)号：US20170309618A9

公开(公告)日：2017-10-26

申请号：US14829487

申请日：2015-08-18

申请人： PATRICK B. SHEA ,  Michael Rennie ,  Sandro J. Di Giacomo

发明人： PATRICK B. SHEA ,  Michael Rennie ,  Sandro J. Di Giacomo

IPC分类号： H01L27/07 ,  H01L29/737 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L27/06 ,  H01L21/8249

CPC分类号： H01L27/0711 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/092 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7378

摘要： A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region.

公开(公告)号：US10312142B2

公开(公告)日：2019-06-04

申请号：US15362400

申请日：2016-11-28

申请人： Christopher F. Kirby ,  Michael Rennie ,  Daniel J. O'Donnell ,  Sandro J. Di Giacomo

发明人： Christopher F. Kirby ,  Michael Rennie ,  Daniel J. O'Donnell ,  Sandro J. Di Giacomo

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311 ,  H01L21/321 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/66 ,  H01L39/12 ,  H01L39/24 ,  H01P3/08 ,  H01P11/00

摘要： A method of forming a superconductor structure is provided. The method comprises forming a superconducting element in a first dielectric layer that has a top surface aligned with the top surface of the first dielectric layer, forming a second dielectric layer over the first dielectric layer and the superconducting element, and forming an opening in the second dielectric layer to a top surface of the superconducting element. The method also comprises performing a cleaning process on the top surface of the superconducting element to remove oxides formed on the top surface of the superconducting element at a first processing stage, forming a protective barrier over the top surface of the superconducting element, and moving the superconductor structure to a second processing stage for further processing.

公开(公告)号：US20180151430A1

公开(公告)日：2018-05-31

申请号：US15362400

申请日：2016-11-28

申请人： Christopher F. KIRBY ,  Michael Rennie ,  Daniel J. O'Donnell ,  Sandro J. Di Giacomo

发明人： Christopher F. KIRBY ,  Michael Rennie ,  Daniel J. O'Donnell ,  Sandro J. Di Giacomo

IPC分类号： H01L21/768 ,  H01L39/24 ,  H01L39/12 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311 ,  H01L21/321 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01P3/08 ,  H01P11/00 ,  H01L23/66

CPC分类号： H01L21/76891 ,  H01L21/02063 ,  H01L21/02074 ,  H01L21/0273 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53285 ,  H01L23/66 ,  H01L39/12 ,  H01L39/2406 ,  H01L2223/6627 ,  H01P3/081 ,  H01P11/003

摘要： A method of forming a superconductor structure is provided. The method comprises forming a superconducting element in a first dielectric layer that has a top surface aligned with the top surface of the first dielectric layer, forming a second dielectric layer over the first dielectric layer and the superconducting element, and forming an opening in the second dielectric layer to a top surface of the superconducting element. The method also comprises performing a cleaning process on the top surface of the superconducting element to remove oxides formed on the top surface of the superconducting element at a first processing stage, forming a protective barrier over the top surface of the superconducting element, and moving the superconductor structure to a second processing stage for further processing.

公开(公告)号：US10312141B2

公开(公告)日：2019-06-04

申请号：US15238394

申请日：2016-08-16

申请人： Christopher F. Kirby ,  Sandro J. Di Giacomo ,  Michael Rennie

发明人： Christopher F. Kirby ,  Sandro J. Di Giacomo ,  Michael Rennie

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/02

摘要： A method is provided of forming a superconductor device interconnect structure. The method includes forming a first dielectric layer overlying a substrate, and forming a superconducting interconnect element in a first dielectric layer, such that the superconducting interconnect element has a top surface aligned with a top surface of the first dielectric layer to form a first interconnect layer. The method also includes performing a plasma clean on a top surface of the first interconnect layer, and depositing a second dielectric layer over the first dielectric layer.

公开(公告)号：US09780285B1

公开(公告)日：2017-10-03

申请号：US15238375

申请日：2016-08-16

申请人： Christopher F. Kirby ,  Michael Rennie ,  Daniel J. O'Donnell

发明人： Christopher F. Kirby ,  Michael Rennie ,  Daniel J. O'Donnell

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L39/22 ,  H01L39/02 ,  H01L39/24

CPC分类号： H01L39/223 ,  H01L39/025 ,  H01L39/2493

摘要： A method is provided of forming a superconductor device interconnect structure. The method includes forming a first dielectric layer overlying a substrate, and forming a base electrode in the first dielectric layer with the base electrode having a top surface aligned with the top surface of the first dielectric layer. The method further comprises forming a Josephson junction (JJ) over the base electrode, depositing a second dielectric layer over the JJ, the base electrode and the first dielectric layer, and forming a first contact through the second dielectric layer to the base electrode to electrically couple the first contact to a first end of the JJ, and a second contact through the second dielectric layer to a second end of the JJ.

公开(公告)号：US20130075862A1

公开(公告)日：2013-03-28

申请号：US13240748

申请日：2011-09-22

申请人： Michael Rennie ,  Thomas J. Knight

发明人： Michael Rennie ,  Thomas J. Knight

IPC分类号： H01L21/20 ,  H01L29/92

CPC分类号： H01L28/90 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are provided for forming a capacitor. In one embodiment, a method comprises providing an insulator material layer over a substrate, etching at least one via in the insulator material layer and depositing a contact material fill in the at least one via to form a first set of contacts. The method further comprises etching the insulator material layer adjacent at least one contact of the first set of contacts to form at least one void, depositing a dielectric material layer over the at least one void and over the first set of contacts and depositing a contact material fill in the at least void to form a second set of contacts.

摘要翻译： 提供了形成电容器的方法。 在一个实施例中，一种方法包括在衬底上提供绝缘体材料层，在绝缘体材料层中蚀刻至少一个通孔，并且在至少一个通孔中沉积接触材料填充物以形成第一组触点。 该方法还包括：蚀刻与第一组触点的至少一个触点相邻的绝缘体材料层，以形成至少一个空隙，在至少一个空隙上并在第一组触点上沉积介电材料层，并沉积触点材料 填写至少空格以形成第二组联系人。

公开(公告)号：US20060084274A1

公开(公告)日：2006-04-20

申请号：US10967869

申请日：2004-10-18

申请人： Michael Rennie ,  Jon Davis ,  Robert Fuller ,  Franz Hagl

发明人： Michael Rennie ,  Jon Davis ,  Robert Fuller ,  Franz Hagl

IPC分类号： H01L21/311

CPC分类号： H01L21/3083 ,  H01L21/3065

摘要： An edge protection process for semiconductor device fabrication includes forming a protective layer on the circumferential edge region of a semiconductor substrate. The semiconductor substrate is placed in a plasma atmosphere and trench structures, such as deep trenches and shallow trench isolation structures are etched in the substrate. The protective layer substantially prevents the etching of the circumferential edge region, such that the formation of black silicon is substantially minimized during the etching process.

摘要翻译： 用于半导体器件制造的边缘保护工艺包括在半导体衬底的周缘区域上形成保护层。 将半导体衬底放置在等离子体气氛中，并且在衬底中蚀刻诸如深沟槽和浅沟槽隔离结构的沟槽结构。 保护层基本上防止了周边边缘区域的蚀刻，使得在蚀刻工艺期间黑色硅的形成基本上被最小化。