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公开(公告)号：US09595563B2
公开(公告)日：2017-03-14
申请号：US14678002
申请日：2015-04-03
Inventor： Satoru Ito , Takumi Mikawa , Kazuhiko Shimakawa
CPC classification number: H01L27/2463 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1675
Abstract: A nonvolatile memory device includes: a pair of first wirings extending in a first direction; a second wiring extending in a second direction crossing the first direction; a pair of third wirings extending in the second direction; and a fourth wiring located between the pair of the third wirings. The nonvolatile memory device has four resistance-change elements each which is provided adjacent to respective four crossing areas in which each of the pair of first wirings intersects with each of the pair of third wirings, and a first contact plug disposed at an intersection of two diagonals of a virtual tetragon defined by the four resistance-change elements. Two transistors arranged in the second direction, among four transistors, share each one first main terminal located between the pair of the first wirings, the shared each one first main terminal being connected to the second wiring.
Abstract translation: 非易失性存储器件包括：沿第一方向延伸的一对第一配线; 沿与所述第一方向交叉的第二方向延伸的第二布线; 一对沿第二方向延伸的第三布线; 以及位于所述一对所述第三配线之间的第四配线。 非易失性存储器件具有四个电阻变化元件，每个电阻变化元件设置在相邻的四个交叉区域附近，其中每对第一布线中的每一对与每对第三布线相交，并且第一接触插塞设置在两个交叉点的交点处 由四个电阻变化元件限定的虚拟四边形的对角线。 在四个晶体管之中沿第二方向布置的两个晶体管共享位于一对第一布线之间的每个第一主端子，共享的每个第一主端子连接到第二布线。
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公开(公告)号：US09053787B2
公开(公告)日：2015-06-09
申请号：US14119936
申请日：2013-03-27
Inventor： Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Akifumi Kawahara
CPC classification number: G11C13/004 , G11C13/0007 , G11C13/0038 , G11C13/0069 , G11C2013/0078 , G11C2013/0083 , G11C2213/15
Abstract: The nonvolatile memory device includes a control circuit that controls a sense amplification circuit and a writing circuit. The control circuit changes a value of at least one of (a) a load current and (b) a forming pulse current or a forming pulse voltage, according to a total number of sneak current paths formed by memory cells each including a variable resistance element in a second resistance state having a low resistance value except a selected memory cell in a memory cell array.
Abstract translation: 非易失性存储器件包括控制读出放大电路和写入电路的控制电路。 控制电路根据由存储单元形成的每个包含可变电阻元件的总体潜流电流路径的总数，改变（a）负载电流和（b）形成脉冲电流或形成脉冲电压中的至少一个的值 在除了存储单元阵列中的所选存储单元之外具有低电阻值的第二电阻状态。
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Patent Agency Ranking
3.发明授权Variable resistance nonvolatile memory device including a variable resistance layer that changes reversibly between a low resistance state and a high resistance state according to an applied electrical signal 有权可变电阻非易失性存储装置包括根据所施加的电信号在低电阻状态和高电阻状态之间可逆地改变的可变电阻层公开(公告)号：US09336881B2
公开(公告)日：2016-05-10
申请号：US14730629
申请日：2015-06-04
Inventor： Kazuhiko Shimakawa , Ryotaro Azuma , Ken Kawai , Shunsaku Muraoka
CPC classification number: G11C13/0069 , G11C13/0007 , G11C2013/0071 , G11C2013/0073 , G11C2013/009 , G11C2213/79 , G11C2213/82
Abstract: A variable resistance nonvolatile memory device includes: a nonvolatile memory element; an NMOS transistor connected to the nonvolatile memory element; a source line connected to the NMOS transistor; a bit line connected to the nonvolatile memory element. When a control circuit causes the nonvolatile memory element to be in the low resistance state, the control circuit controls to flow a first current from a first voltage source to a reference potential point, and applies a first gate voltage to a gate of a NMOS transistor, and when the control circuit causes the nonvolatile memory element to be in the high resistance state, the control circuit controls to flow a second current from a second voltage source to the reference potential point, and applies a second gate voltage to the gate of the NMOS transistor, the second gate voltage being lower than the first gate voltage.
Abstract translation: 一种可变电阻非易失性存储器件包括：非易失性存储元件; 连接到非易失性存储元件的NMOS晶体管; 连接到NMOS晶体管的源极线; 连接到非易失性存储元件的位线。 当控制电路使非易失性存储元件处于低电阻状态时，控制电路控制第一电流从第一电压源流向基准电位点，并将第一栅极电压施加到NMOS晶体管的栅极 并且当控制电路使非易失性存储元件处于高电阻状态时，控制电路控制将第二电流从第二电压源流向基准电位点，并将第二栅极电压施加到栅极 NMOS晶体管，第二栅极电压低于第一栅极电压。
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4.发明授权Write method for writing to variable resistance nonvolatile memory element and variable resistance nonvolatile memory device 有权写入可变电阻非易失性存储器元件和可变电阻非易失性存储器件的写入方法公开(公告)号：US09202565B2
公开(公告)日：2015-12-01
申请号：US14118635
申请日：2013-03-13
Inventor： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0007 , G11C13/0011 , G11C13/0033 , G11C13/0097 , G11C2013/0092 , G11C2213/55
Abstract: A write method for writing to a variable resistance nonvolatile memory element, comprising applying a set of strong recovery-voltage pulses at least once to the variable resistance nonvolatile memory element when it is determined that the resistance state of the variable resistance nonvolatile memory element fails to change to a second resistance state, remaining in a first resistance state, the set of strong recovery-voltage pulses including pulses: (1) a first strong recovery-voltage pulse which has a greater amplitude than a normal second voltage for changing the resistance state to the first resistance state, and has the same polarity as the second voltage; and (2) a second strong recovery-voltage pulse which follows the first strong recovery-voltage pulse and has a longer pulse width than the pulse width of the normal first voltage for changing the resistance state to the second resistance state, and has the same polarity as the first voltage.
Abstract translation: 一种用于写入可变电阻非易失性存储元件的写入方法，包括当确定可变电阻非易失性存储元件的电阻状态不能够时，将至少一次的一组强恢复电压脉冲施加到可变电阻非易失性存储元件 改变为第二电阻状态，保持在第一电阻状态，包括脉冲的强恢复电压脉冲集合：（1）具有比用于改变电阻状态的正常第二电压更大的幅度的第一强恢复电压脉冲 并具有与第二电压相同的极性; 和（2）第二强恢复电压脉冲，其跟随第一强恢复电压脉冲并且具有比用于将电阻状态改变为第二电阻状态的正常第一电压的脉冲宽度更长的脉冲宽度，并且具有相同 极性作为第一电压。
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公开(公告)号：US09053788B2
公开(公告)日：2015-06-09
申请号：US14122714
申请日：2013-03-27
Inventor： Ryotaro Azuma , Kazuhiko Shimakawa
CPC classification number: G11C13/004 , G11C13/0007 , G11C13/0064 , G11C2013/0054 , G11C2213/15 , G11C2213/71 , G11C2213/72
Abstract: A cross-point memory device including memory cells each includes: a variable resistance element that reversibly changes at least between a low resistance state and a high resistance state; and a current steering element that has nonlinear current-voltage characteristics, and the cross-point memory device comprises a read circuit which includes: a reference voltage generation circuit which comprises at least the current steering element; a differential amplifier circuit which performs current amplification on an output voltage in the reference voltage generation circuit; a feedback controlled bit line voltage clamp circuit which sets the low voltage side reference voltage to increase with an output of the differential amplifier circuit; and a sense amplifier circuit which determines a resistance state of a selected memory cell according to an amount of current flowing through the selected memory cell.
Abstract translation: 包括存储单元的交叉点存储器件每个都包括：至少在低电阻状态和高电阻状态之间可逆地改变的可变电阻元件; 以及具有非线性电流 - 电压特性的电流导向元件，并且所述交叉点存储器件包括读取电路，所述读取电路包括：至少包括所述电流转向元件的参考电压产生电路; 对基准电压产生电路中的输出电压进行电流放大的差分放大电路; 反馈控制的位线电压钳位电路，其利用差分放大器电路的输出设定低电压侧参考电压增加; 以及读出放大器电路，其根据流过选择的存储单元的电流量来确定所选存储单元的电阻状态。
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6.发明授权Variable resistance nonvolatile memory element writing method and variable resistance nonvolatile memory device 有权可变电阻非易失性存储元件写入方法和可变电阻非易失性存储器件公开(公告)号：US09001557B2
公开(公告)日：2015-04-07
申请号：US13990209
申请日：2012-11-21
Inventor： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh , Yuichiro Ikeda
CPC classification number: G11C13/0069 , G11C13/00 , G11C13/004 , G11C13/0064 , G11C2013/0073 , G11C2013/0092
Abstract: Provided is a method of writing to a variable resistance nonvolatile memory element which is capable of both improving retention characteristics and enlarging a window of operation. In the method of writing, to write “1” data (LR), first a weak HR writing process is performed in which a weak HR writing voltage pulse set for changing the variable resistance nonvolatile memory element to an intermediate resistance state is applied and, subsequently, a LR writing process is performed in which a LR writing voltage pulse set for changing the variable resistance nonvolatile memory element from the intermediate resistance state to a LR state is applied.
Abstract translation: 提供一种写入能够改善保持特性和扩大操作窗口的可变电阻非易失性存储元件的方法。 在写入方法中，为了写入“1”数据（LR），首先执行将用于将可变电阻非易失性存储元件变更为中间电阻状态而设定的弱的HR写入电压脉冲的弱的HR写入处理， 随后，执行LR写入处理，其中设置用于将可变电阻非易失性存储元件从中间电阻状态改变为LR状态的LR写入电压脉冲。
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7.发明授权公开(公告)号：US09484090B2
公开(公告)日：2016-11-01
申请号：US14635297
申请日：2015-03-02
Inventor： Yuhei Yoshimoto , Kazuhiko Shimakawa , Ken Kawai , Ryotaro Azuma
CPC classification number: G11C13/004 , G11C7/062 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C13/0061 , G11C13/0069 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/70 , G11C2013/005 , G11C2013/0054 , G11C2013/0073 , G11C2013/009 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146
Abstract: A selection circuit that selects a memory cell from a memory cell array and a read circuit for reading a resistance state of a resistance change element in the selected memory cell are provided. In memory cells of odd-numbered-layer and even-numbered-layer memory cell arrays that constitute a multilayer memory cell array, each memory cell in any of the layers has a selection element, a first electrode, a first resistance change layer, a second resistance change layer, and a second electrode that are disposed in the same order. Whether the selected memory cell is located in any layer of the multilayer memory cell array, the read circuit applies a voltage to the selected memory cell to perform the reading operation. The voltage applied to the selected memory cell causes the second electrode to become positive with reference to the first electrode in the selected memory cell.
Abstract translation: 提供从存储单元阵列选择存储单元的选择电路和用于读取所选存储单元中的电阻变化元件的电阻状态的读取电路。 在构成多层存储单元阵列的奇数层和偶数层存储单元阵列的存储单元中，任何层中的每个存储单元都具有选择元件，第一电极，第一电阻改变层， 第二电阻变化层和第二电极。 所选择的存储单元是否位于多层存储单元阵列的任何层中，读取电路向所选存储单元施加电压以执行读取操作。 施加到所选择的存储单元的电压使得第二电极参照所选择的存储单元中的第一电极变为正。
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