公开(公告)号：US09595563B2

公开(公告)日：2017-03-14

申请号：US14678002

申请日：2015-04-03

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Satoru Ito ,  Takumi Mikawa ,  Kazuhiko Shimakawa

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2463 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1675

Abstract: A nonvolatile memory device includes: a pair of first wirings extending in a first direction; a second wiring extending in a second direction crossing the first direction; a pair of third wirings extending in the second direction; and a fourth wiring located between the pair of the third wirings. The nonvolatile memory device has four resistance-change elements each which is provided adjacent to respective four crossing areas in which each of the pair of first wirings intersects with each of the pair of third wirings, and a first contact plug disposed at an intersection of two diagonals of a virtual tetragon defined by the four resistance-change elements. Two transistors arranged in the second direction, among four transistors, share each one first main terminal located between the pair of the first wirings, the shared each one first main terminal being connected to the second wiring.

Abstract translation: 非易失性存储器件包括：沿第一方向延伸的一对第一配线; 沿与所述第一方向交叉的第二方向延伸的第二布线; 一对沿第二方向延伸的第三布线; 以及位于所述一对所述第三配线之间的第四配线。 非易失性存储器件具有四个电阻变化元件，每个电阻变化元件设置在相邻的四个交叉区域附近，其中每对第一布线中的每一对与每对第三布线相交，并且第一接触插塞设置在两个交叉点的交点处 由四个电阻变化元件限定的虚拟四边形的对角线。 在四个晶体管之中沿第二方向布置的两个晶体管共享位于一对第一布线之间的每个第一主端子，共享的每个第一主端子连接到第二布线。

公开(公告)号：US09054305B2

公开(公告)日：2015-06-09

申请号：US14207763

申请日：2014-03-13

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Satoru Ito ,  Yoshio Kawashima ,  Yukio Hayakawa ,  Takumi Mikawa

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/22

CPC classification number: H01L45/1253 ,  H01L27/222 ,  H01L45/04 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

Abstract: A nonvolatile memory device includes a plurality of nonvolatile memory elements each having an upper electrode, a variable resistance layer, and a lower electrode; a first insulating layer embedding the plurality of nonvolatile memory elements, and ranging from a lowermost part of the lower electrode to a position higher than an uppermost part of the upper electrode in each of the nonvolatile memory elements; a second insulating layer being formed on the first insulating layer, and having an average size of vacancies larger than an average size of vacancies included in the first insulating layer, or having an average carbon concentration higher than an average carbon concentration of the first insulating layer; and a conductive layer penetrating the second insulating layer and a part of the first insulating layer and being connected to at least one of the upper electrodes included in the nonvolatile memory elements.

Abstract translation: 非易失性存储器件包括多个非易失性存储元件，每个非易失性存储元件具有上电极，可变电阻层和下电极; 嵌入所述多个非易失性存储元件的第一绝缘层，并且在所述非易失性存储元件的每一个中，从所述下电极的最下部分到高于所述上电极的最上部的位置; 第二绝缘层，形成在第一绝缘层上，并且具有比第一绝缘层中包含的空位的平均尺寸大的空位的平均尺寸，或平均碳浓度高于第一绝缘层的平均碳浓度 ; 以及贯穿所述第二绝缘层和所述第一绝缘层的一部分并且连接到包括在所述非易失性存储元件中的至少一个上电极的导电层。

公开(公告)号：US09570682B2

公开(公告)日：2017-02-14

申请号：US14879625

申请日：2015-10-09

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Takumi Mikawa ,  Takashi Okada

IPC: H01L45/00 ,  H01L27/10

CPC classification number: H01L45/1608 ,  H01L27/101 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1675

Abstract: Provided are a variable resistance semiconductor memory device which changes its resistance without being affected by an underlying layer and is suitable as a memory device of increased capacity, and a method of manufacturing the same. The semiconductor memory device in the present invention includes: a first contact plug formed inside a first contact hole penetrating through a first interlayer insulating layer; a lower electrode having a flat top surface and is thicker above the first interlayer insulating layer than above the first contact plug; a variable resistance layer; and an upper electrode. The lower electrode, the variable resistance layer, and the upper electrode compose a variable resistance element.

Abstract translation: 提供一种可变电阻半导体存储器件，其改变其电阻而不受下层的影响，并且适合作为增加容量的存储器件及其制造方法。 本发明的半导体存储器件包括：形成在穿过第一层间绝缘层的第一接触孔内的第一接触插塞; 下电极，其具有平坦的顶表面，并且比所述第一接触插塞上方更厚于所述第一层间绝缘层之上; 可变电阻层; 和上电极。 下电极，可变电阻层和上电极构成可变电阻元件。

公开(公告)号：US09082974B2

公开(公告)日：2015-07-14

申请号：US13983071

申请日：2012-09-20

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Takumi Mikawa ,  Hideaki Murase

IPC: H01L21/20 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/16 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

Abstract: A nonvolatile memory element includes: a lower electrode formed above a substrate; a first variable resistance layer formed above the lower electrode and comprising a first metal oxide; a second variable resistance layer formed above the first variable resistance layer and comprising a second metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first metal oxide; and an upper electrode formed above the second variable resistance layer. A single step is formed in an interface between the first variable resistance layer and the second variable resistance layer. The second variable resistance layer is formed to cover the step and have, above the step, a bend (or stepped portion) covering the step. The bend, seen from above, has only one corner in a surface of the second variable resistance layer.

Abstract translation: 非易失性存储元件包括：形成在衬底上的下电极; 第一可变电阻层，形成在所述下电极上并包括第一金属氧化物; 第二可变电阻层，其形成在所述第一可变电阻层上方，并且包含氧缺乏程度低于所述第一金属氧化物的缺氧程度的第二金属氧化物; 以及形成在第二可变电阻层上方的上电极。 在第一可变电阻层和第二可变电阻层之间的界面中形成单个步骤。 形成第二可变电阻层以覆盖该台阶，并且在该台阶之上具有覆盖台阶的弯曲部（或阶梯部）。 从上方看到的弯曲部在第二可变电阻层的表面中仅具有一个角部。

公开(公告)号：US09006701B2

公开(公告)日：2015-04-14

申请号：US14054538

申请日：2013-10-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Satoru Ito ,  Takumi Mikawa

IPC: H01L47/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L45/06 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

Abstract: A non-volatile memory device comprises first wires on and above a first plane; second wires extending in a direction crossing the first wires, on and above a second plane, third wires extending in parallel with the second wires on and above a fourth plane, and memory cells provided to correspond to three-dimensional cross-points of the first wires and the third wires, respectively, each of the memory cells including a transistor and a variable resistance element, the transistor including a first main electrode, a second main electrode, and a control electrode, the variable resistance element being placed on and above a third plane and including a lower electrode, an upper electrode and a variable resistance layer, wherein the upper electrode is connected to corresponding one of the third wires; and further comprises a first contact plug extending from the first main electrode to the second plane and connected to corresponding one of the second wires; a second contact plug extending from the second main electrode to the second plane; and a third contact plug extending from the second contact plug and connected to the lower electrode; wherein the second main electrode and the lower electrode are connected to each other via the second contact plug and the third contact plug.

Abstract translation: 非易失性存储器件包括在第一平面上和之上的第一布线; 沿着与第一布线交叉的方向延伸的第二布线，在第二平面上和上方延伸的第三布线，与第四布线上和第四平面上的第二布线平行延伸的第三布线，以及提供以对应于第一布线的第三布线的三维交叉点的存储单元 线和第三线，每个存储单元包括晶体管和可变电阻元件，所述晶体管包括第一主电极，第二主电极和控制电极，所述可变电阻元件置于 第三平面，并且包括下电极，上电极和可变电阻层，其中上电极连接到相应的一个第三电线; 并且还包括从所述第一主电极延伸到所述第二平面并连接到所述第二电线中的相应一个的第一接触插塞; 从所述第二主电极延伸到所述第二平面的第二接触插塞; 以及从所述第二接触插头延伸并连接到所述下电极的第三接触插塞; 其中所述第二主电极和所述下电极经由所述第二接触插塞和所述第三接触插塞彼此连接。