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公开(公告)号:US20230164462A1
公开(公告)日:2023-05-25
申请号:US18100401
申请日:2023-01-23
Inventor: Naoki TORAZAWA , Tatsuya KABE , Yutaka HIROSE
IPC: H04N25/77 , H01L27/146
CPC classification number: H04N25/77 , H01L27/14643
Abstract: A photodetector includes a semiconductor substrate; a photoelectric converter in the semiconductor substrate; and a condenser light-transmissive and opposed to the photoelectric converter. The condenser includes: an inorganic material layer at least partially overlapping the photoelectric converter in a plan view; and an inorganic material layer covering the inorganic material layer and having a refractive index lower than a refractive index of the inorganic material layer.
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公开(公告)号:US20220014701A1
公开(公告)日:2022-01-13
申请号:US17486495
申请日:2021-09-27
Inventor: Tatsuya KABE , Hideyuki ARAI , Hisashi AIKAWA , Yuki SUGIURA , Akito INOUE , Mitsuyoshi MORI , Kentaro NAKANISHI , Yusuke SAKATA
IPC: H04N5/378 , H01L27/146 , H04N5/374
Abstract: A light detector is configured such that a light receiving portion having APDs and a peripheral circuit portion are provided on a first principal surface of a p-type semiconductor substrate, and further includes a back electrode provided on a second principal surface of the semiconductor substrate and a p-type first separation portion provided between the light receiving portion and the peripheral circuit portion. The APD has, on a first principal surface side, an n-type region and a p-epitaxial layer contacting the n-type region in a Z-direction. The peripheral circuit portion has an n-type MISFET provided at a p-well and an n-well provided to surround side and bottom portions of the p-well.
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公开(公告)号:US20240121530A1
公开(公告)日:2024-04-11
申请号:US18541932
申请日:2023-12-15
Inventor: Tatsuya KABE , Hideyuki ARAI , Hisashi AIKAWA , Yuki SUGIURA , Akito INOUE , Mitsuyoshi MORI , Kentaro NAKANISHI , Yusuke SAKATA
IPC: H04N25/75 , H01L27/146 , H04N25/766
CPC classification number: H04N25/75 , H01L27/14612 , H01L27/14636 , H01L27/14643 , H04N25/766
Abstract: A light detector is configured such that a light receiving portion having APDs and a peripheral portion are provided on a first principal surface of a p-type semiconductor substrate, and further includes a back electrode provided on a second principal surface of the semiconductor substrate and a p-type first separation portion provided between the light receiving portion and the peripheral portion. The APD has, on a first principal surface side, an n-type region and a p-epitaxial layer contacting the n-type region in a Z-direction. The peripheral portion has an n-type MISFET provided at a p-well and an n-well provided to surround entire side and bottom portions of the p-well.
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公开(公告)号:US20240038726A1
公开(公告)日:2024-02-01
申请号:US18264194
申请日:2021-12-21
Inventor: Koji OBATA , Masaru SASAGO , Masamichi NAKAGAWA , Tatsuya KABE , Hiroyuki GOMYO , Masatomo MITSUHASHI , Yutaka SONODA
IPC: H01L25/065 , H01L23/48 , H01L23/00 , H01L27/02 , H10B80/00
CPC classification number: H01L25/0657 , H01L23/481 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/16 , H01L27/0207 , H01L24/08 , H10B80/00 , H01L2225/0651 , H01L2225/06513 , H01L2225/06524 , H01L2225/06544 , H01L2924/1431 , H01L2924/1434 , H01L2224/16146 , H01L2224/48225 , H01L2224/32225 , H01L2224/73207 , H01L2224/73253 , H01L2224/73265 , H01L2224/08145
Abstract: An AI module includes a first semiconductor chip. The first semiconductor chip includes a plurality of operation blocks each of which performs a predetermined operation and a plurality of memory blocks each including memory. The plurality of operation blocks and the plurality of memory blocks are arranged in a checkered pattern or in a striped pattern in plan view.
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公开(公告)号:US20230244262A1
公开(公告)日:2023-08-03
申请号:US18299007
申请日:2023-04-11
Inventor: Hiroshi KOSHIDA , Shinzo KOYAMA , Tatsuya KABE , Masaki TAMARU
CPC classification number: G05F3/265 , G01J1/44 , H01L27/082
Abstract: A substrate current suppression circuit includes: a fixed voltage line that supplies a fixed voltage to the collectors of the third and fourth transistors. The fixed voltage is a voltage higher than the base voltage of the third and fourth transistors when the first polarity is p type, and is a voltage lower than the base voltage when the first polarity is n type.
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公开(公告)号:US20220310674A1
公开(公告)日:2022-09-29
申请号:US17840167
申请日:2022-06-14
Inventor: Kentaro NAKANISHI , Tatsuya KABE , Mitsuyoshi MORI , Shigeru SAITOU
IPC: H01L27/146
Abstract: A semiconductor device includes a semiconductor substrate a pixel region in which an APD is disposed, and a logic region different from the pixel region; a transistor which is disposed in the logic region and includes a sidewall made of an insulating material; an anti-reflective film which is disposed above a main surface of the semiconductor substrate in the pixel region and is made of the insulating material; and a first liner film which is disposed above the main surface of the semiconductor substrate in the logic region and is made of the insulating material. The anti-reflective film and the first liner film are integrally formed. The thickness of the anti-reflective film is larger than or equal to the sum of the thickness of the sidewall and the thickness of the first liner film.
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公开(公告)号:US20160043060A1
公开(公告)日:2016-02-11
申请号:US14920289
申请日:2015-10-22
Inventor: Tatsuya KABE , Hideyuki ARAI
IPC: H01L25/065 , H01L23/00 , H01L23/522
CPC classification number: H01L25/0657 , H01L21/76898 , H01L23/5223 , H01L23/5227 , H01L24/05 , H01L24/08 , H01L24/80 , H01L27/0688 , H01L28/20 , H01L28/40 , H01L2224/05568 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05684 , H01L2224/0603 , H01L2224/06051 , H01L2224/08145 , H01L2224/80097 , H01L2224/80201 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01074 , H01L2924/0132 , H01L2924/05042 , H01L2924/0534 , H01L2924/05442 , H01L2924/0549 , H01L2924/00014 , H01L2924/00012
Abstract: A semiconductor device includes: a first substrate including a first surface layer that includes first and second electrodes; a second substrate including a second surface layer that includes third and fourth electrodes, and directly bonded to the first substrate such that the second surface layer is in contact with the first surface layer; and a functional film provided between the second and fourth electrodes. The first and third electrodes are bonded together so as to be in contact with each other, and the second electrode, the functional film, and the fourth electrode constitute a passive element.
Abstract translation: 一种半导体器件包括:第一衬底,包括包括第一和第二电极的第一表面层; 第二基板,其包括包括第三和第四电极的第二表面层,并且直接接合到第一基板,使得第二表面层与第一表面层接触; 以及设置在第二和第四电极之间的功能膜。 第一和第三电极彼此接触结合在一起,并且第二电极,功能膜和第四电极构成无源元件。
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