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公开(公告)号:US20240038726A1
公开(公告)日:2024-02-01
申请号:US18264194
申请日:2021-12-21
Inventor: Koji OBATA , Masaru SASAGO , Masamichi NAKAGAWA , Tatsuya KABE , Hiroyuki GOMYO , Masatomo MITSUHASHI , Yutaka SONODA
IPC: H01L25/065 , H01L23/48 , H01L23/00 , H01L27/02 , H10B80/00
CPC classification number: H01L25/0657 , H01L23/481 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/16 , H01L27/0207 , H01L24/08 , H10B80/00 , H01L2225/0651 , H01L2225/06513 , H01L2225/06524 , H01L2225/06544 , H01L2924/1431 , H01L2924/1434 , H01L2224/16146 , H01L2224/48225 , H01L2224/32225 , H01L2224/73207 , H01L2224/73253 , H01L2224/73265 , H01L2224/08145
Abstract: An AI module includes a first semiconductor chip. The first semiconductor chip includes a plurality of operation blocks each of which performs a predetermined operation and a plurality of memory blocks each including memory. The plurality of operation blocks and the plurality of memory blocks are arranged in a checkered pattern or in a striped pattern in plan view.