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公开(公告)号：US20190334745A1
公开(公告)日：2019-10-31
申请号：US16504958
申请日：2019-07-08
Applicant: Oracle International Corporation
Inventor： Rajesh Kumar , Seno Judaprawira , Dawei Huang
Abstract: A reference generator for use with serial link data communication is disclosed. Broadly speaking, a decision circuit may perform a comparison between a particular data symbol included in a serial data stream and a difference between a voltage level of a first signal and a voltage level of a second signal, and generate an output data value based on a result of the comparison. A reference generator circuit may selectively sink a first current value from either the first signal or the second signal based upon another output data value generated from another data symbol included in the serial data stream that was received prior to the particular data symbol.
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公开(公告)号：US20190104088A1
公开(公告)日：2019-04-04
申请号：US15722349
申请日：2017-10-02
Applicant: Oracle International Corporation
Inventor： Zuxu Qin , Baoqing Huang , Dawei Huang , Kuai Yin , Maoqing Yao , Philip Kwan
IPC: H04L12/935 , H04L9/06 , B23P19/04
Abstract: Embodiments include systems and methods for transmitting data over high-speed data channels in context of serializer/deserializer circuits. Some embodiments include a novel full-rate source-series-terminated (SST) transmitter driver architecture with output charge sharing isolation. Certain implementations have a programmable floating tap (e.g., in addition to standard taps) with both positive and negative FIR values and cursor reduction, which can help achieve large FIR range and high channel equalization capability. Some embodiments operate with multi-phase clocking having phased clock error correction, which can facilitate operation with low-jitter and low-DCD clocks. Some implementations also include novel output inductor structures that are disposed to partially overlap output interface bumps.
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公开(公告)号：US20180174161A1
公开(公告)日：2018-06-21
申请号：US15385621
申请日：2016-12-20
Applicant: Oracle International Corporation
Inventor： Natalie Shuchyng You , Yizhou Jiang , Wenhua Li , Dawei Huang , Vivek Nama
CPC classification number: G06Q30/0201 , G06F7/026 , G06Q50/01
Abstract: A social media enrichment framework is described herein. In one or more embodiments, the framework is configured to store a set of interface endpoints for accessing different sources of analytic metadata. The framework further stores a set of mappings between social media object types and interface endpoints. Responsive to receiving a social media object having a particular social media object type, the framework identifies, within the set of mappings, a mapping between the particular social media object type and at least one interface endpoint in the set of interface endpoints. The framework then obtains, from one or more sources using the at least one interface endpoint, a set of one or more metrics relevant to the social media object and stores the set of one or more metrics in association with the social media object.
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公开(公告)号：US09921899B2
公开(公告)日：2018-03-20
申请号：US14575590
申请日：2014-12-18
Applicant: Oracle International Corporation
Inventor： Michelle Wong , Dawei Huang , Thomas Wicki , Albert Martin
CPC classification number: G06F11/076 , G06F11/0706 , G06F11/1004 , H04L1/00 , H04L7/00
Abstract: A serial link data monitoring apparatus for targeting a given Bit Error Rate (BER) for stable serial link data communication is disclosed. An interface unit may be configured to receive data via a serial interface, and circuitry may be configured to monitor errors in the data. The circuitry may be further configured to perform one or more first training operations in response to a determination that the number of errors detected in the data is greater than a first threshold value, and perform a second training operation in response to a determination that a number of first training operations performed in a predetermined period of time is greater than a second threshold value. An amount of time to perform the second training operation may be greater than an amount of time to perform a given one of the first training operations.
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公开(公告)号：US09917607B1
公开(公告)日：2018-03-13
申请号：US15449619
申请日：2017-03-03
Applicant: Oracle International Corporation
Inventor： Xun Zhang , Dawei Huang , Jianghui Su , Chaitanya Palusa
CPC classification number: H04B1/16 , H03G3/3078 , H03G2201/706 , H03M1/66 , H04L25/03057
Abstract: Embodiments include systems and methods for baseline wander correction gain adaptation in receiver circuits. Some embodiments operate in context of an alternating current coupled transceiver communicating data signals over a high-speed transmission channel, such that the receiver system includes an AC-coupled data input and a feedback loop with a data slicer and an error slicer. A baseline wander correction (BWC) circuit can be part of the feedback loop and can generate a feedback signal corresponding to low-pass-filtered bits data from the data slicer output and having a gain generated according to pattern-filtered error data from the error slicer output. For example, gain adaptation is performed according to error information corresponding to a detected relatively high-frequency data pattern following a long low-frequency pattern.
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Patent Agency Ranking
公开(公告)号：US09893878B1
公开(公告)日：2018-02-13
申请号：US15459715
申请日：2017-03-15
Applicant: Oracle International Corporation
Inventor： Long Kong , Ben Li Chen , Philip Kwan , Zuxu Qin , Dawei Huang
Abstract: Embodiments include systems and methods for on-chip random jitter (RJ) measurement in a clocking circuit (e.g., in a phase-locked loop of a serializer/deserializer circuit). Some embodiments determine a reference delay code sweep window to capture at least a candidate RJ range of a feedback clock signal, the reference delay code sweep window comprising a sequence of reference delay codes. A distribution of one-scores can be computed over the reference delay code sweep window, so that the distribution indicates a relatively likelihood, for each reference delay code, of obtaining a ‘1’ sample when sampling the feedback clock signal according to the delayed clock signal (delayed by an amount according to the reference delay code). The distribution can be transformed into a time domain by computing code offset times for the reference delay codes. A RJ output can be computed as a function of the distribution in the time domain.
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公开(公告)号：US09231752B1
公开(公告)日：2016-01-05
申请号：US14639886
申请日：2015-03-05
Applicant: ORACLE INTERNATIONAL CORPORATION
Inventor： Yan Yan , Ali Gokhan Ileri , Jianghui Su , Dawei Huang , Xun Zhang , Sifang You
CPC classification number: H04L7/0016 , H03L7/0807 , H03L7/0814 , H04L7/0062 , H04L7/033
Abstract: Embodiments include systems and methods for increasing frequency offset tracking in clock data recovery (CDR) systems. For example, in asynchronous clocking environments, the receiver-side clock frequency can be offset from the transmitter-side clock. While traditional CDR systems can handle some amount of offset, they are typically ineffective at accurately adapting the receiver-side clocking to an optimal data sampling rate when the offset is excessive. Embodiments include a CDR frequency offset adaptation loop that generates an adaptation signal, which can be monitored to detect an adaptation error arising from excessive frequency offset. In response to the detecting, an offset seed can be selected and injected into the frequency offset adaptation loop, thereby reinitializing the frequency offset adaptation loop with a less stressful seed.
Abstract translation: 实施例包括用于在时钟数据恢复（CDR）系统中增加频率偏移跟踪的系统和方法。 例如，在异步时钟环境中，接收机侧时钟频率可以偏离发射机侧时钟。 虽然传统的CDR系统可以处理一些偏移量，但是当偏移量过大时，它们通常无效地将接收机侧时钟精确地适配到最佳数据采样率。 实施例包括产生自适应信号的CDR频率偏移适配环路，其可以被监视以检测由过多频率偏移引起的适应误差。 响应于检测，可以选择偏移种子并将其注入到频率偏移适配环路中，从而以较小的压力种子重新初始化频率偏移适配环路。
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公开(公告)号：US09184906B1
公开(公告)日：2015-11-10
申请号：US14492420
申请日：2014-09-22
Applicant: ORACLE INTERNATIONAL CORPORATION
Inventor： Jihong Min , Dawei Huang , Jianghui Su , Hongtao Zhang
IPC: H04L7/00
CPC classification number: H04L7/0334 , H04L7/0016 , H04L7/0062 , H04L7/0087
Abstract: Embodiments include systems and methods for using generalized pulse amplitude modulation (PAM-X) signaling with an at-rate not-return-to-zero (NRZ) clock data recovery (CDR) system. Some implementations include dual-mode signaling for an at-rate CDR (e.g., using standard NRZ signaling at lower operating frequencies and pseudo-NRZ signaling derived from PAM-X signaling at higher operating frequencies. Embodiments derive an apparent direction of signal transition from PAM-X signaling. The direction can be used to calculate pseudo-NRZ values. For example, when the PAM-X signal transitions in an upward direction, a pseudo-current NRZ value and a pseudo-previous NRZ value of ‘−1’ and ‘+1’ can be generated, respectively. An at-rate NRZ CDR can use the pseudo-NRZ values and a derived error value to make an offset determination. The offset determination can then be used to offset a generated clock signal in the CDR system.
Abstract translation: 实施例包括用于使用通率不归零（NRZ）时钟数据恢复（CDR）系统的广义脉冲幅度调制（PAM-X）信令的系统和方法。 一些实现方案包括用于速率CDR的双模式信令（例如，在较低工作频率下使用标准NRZ信令和在较高工作频率下从PAM-X信令导出的伪NRZ信令。实施例导出来自PAM的信号转换的明显方向 -X信号，该方向可用于计算伪NRZ值，例如，当PAM-X信号向上转换时，伪电流NRZ值和伪前NRZ值为“-1”， 可以分别产生'+1'，高速NRZ CDR可以使用伪NRZ值和派生误差值进行偏移确定，然后可以使用偏移确定来补偿CDR中产生的时钟信号 系统。
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公开(公告)号：US11558223B2
公开(公告)日：2023-01-17
申请号：US17648899
申请日：2022-01-25
Applicant: Oracle International Corporation
Inventor： Xun Zhang , Chaitanya Palusa , Dawei Huang , Muthukumar Vairavan , Jianghui Su
Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.
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公开(公告)号：US10380610B2
公开(公告)日：2019-08-13
申请号：US15385621
申请日：2016-12-20
Applicant: Oracle International Corporation
Inventor： Natalie Shuchyng You , Yizhou Jiang , Wenhua Li , Dawei Huang , Vivek Nama
Abstract: A social media enrichment framework is described herein. In one or more embodiments, the framework is configured to store a set of interface endpoints for accessing different sources of analytic metadata. The framework further stores a set of mappings between social media object types and interface endpoints. Responsive to receiving a social media object having a particular social media object type, the framework identifies, within the set of mappings, a mapping between the particular social media object type and at least one interface endpoint in the set of interface endpoints. The framework then obtains, from one or more sources using the at least one interface endpoint, a set of one or more metrics relevant to the social media object and stores the set of one or more metrics in association with the social media object.
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