公开(公告)号：US20150015315A1

公开(公告)日：2015-01-15

申请号：US13937424

申请日：2013-07-09

Applicant: Oracle International Corporation

Inventor： Zuxu Qin ,  Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Baoqing Huang ,  Yan Yan

IPC: H03K7/08

CPC classification number: H03K7/08 ,  H03K5/1565

Abstract: A method and apparatus for duty cycle distortion compensation is disclosed. In one embodiment, an integrated circuit includes a differential signal transmitter having a main data path and a compensation data path. The main data path includes a first and second differential driver circuits each having output terminals coupled to a differential output. A transmission controller is configured to transmit data into the main and compensation data paths, the data corresponding to pairs of sequentially transmitted bits including an odd data bit followed by an even data bit, and further configured to determine respective duty cycle widths for each of the odd and even data bits as received by the transmission controller. The transmission controller is configured to cause the first and second driver circuits to equalize the respective duty cycle widths of the odd and even data bits, as transmitted, based their respective duty cycle widths as received.

Abstract translation: 公开了一种用于占空比失真补偿的方法和装置。 在一个实施例中，集成电路包括具有主数据路径和补偿数据路径的差分信号发送器。 主数据路径包括具有耦合到差分输出的输出端的第一和第二差分驱动器电路。 发送控制器被配置为将数据发送到主和补偿数据路径中，数据对应于顺序发送的比特对，包括奇数数据位，后跟偶数数据位，并进一步被配置为确定各个占空比宽度 由传输控制器接收的奇数和偶数数据位。 传输控制器被配置为使得第一和第二驱动器电路基于其所接收的各自的占空比宽度来均衡发送的奇数和偶数数据位的相应占空比宽度。

公开(公告)号：US20190104088A1

公开(公告)日：2019-04-04

申请号：US15722349

申请日：2017-10-02

Applicant: Oracle International Corporation

Inventor： Zuxu Qin ,  Baoqing Huang ,  Dawei Huang ,  Kuai Yin ,  Maoqing Yao ,  Philip Kwan

IPC: H04L12/935 ,  H04L9/06 ,  B23P19/04

Abstract: Embodiments include systems and methods for transmitting data over high-speed data channels in context of serializer/deserializer circuits. Some embodiments include a novel full-rate source-series-terminated (SST) transmitter driver architecture with output charge sharing isolation. Certain implementations have a programmable floating tap (e.g., in addition to standard taps) with both positive and negative FIR values and cursor reduction, which can help achieve large FIR range and high channel equalization capability. Some embodiments operate with multi-phase clocking having phased clock error correction, which can facilitate operation with low-jitter and low-DCD clocks. Some implementations also include novel output inductor structures that are disposed to partially overlap output interface bumps.

公开(公告)号：US10257121B1

公开(公告)日：2019-04-09

申请号：US15722349

申请日：2017-10-02

Applicant: Oracle International Corporation

Inventor： Zuxu Qin ,  Baoqing Huang ,  Dawei Huang ,  Kuai Yin ,  Maoqing Yao ,  Philip Kwan

IPC: H04L9/06 ,  B23P19/04 ,  H04L12/935

Abstract: Embodiments include systems and methods for transmitting data over high-speed data channels in context of serializer/deserializer circuits. Some embodiments include a novel full-rate source-series-terminated (SST) transmitter driver architecture with output charge sharing isolation. Certain implementations have a programmable floating tap (e.g., in addition to standard taps) with both positive and negative FIR values and cursor reduction, which can help achieve large FIR range and high channel equalization capability. Some embodiments operate with multi-phase clocking having phased clock error correction, which can facilitate operation with low-jitter and low-DCD clocks. Some implementations also include novel output inductor structures that are disposed to partially overlap output interface bumps.

公开(公告)号：US08994427B2

公开(公告)日：2015-03-31

申请号：US13937424

申请日：2013-07-09

Applicant: Oracle International Corporation

Inventor： Zuxu Qin ,  Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Baoqing Huang ,  Yan Yan

IPC: H03K7/08

CPC classification number: H03K7/08 ,  H03K5/1565

Abstract: A method and apparatus for duty cycle distortion compensation is disclosed. In one embodiment, an integrated circuit includes a differential signal transmitter having a main data path and a compensation data path. The main data path includes a first and second differential driver circuits each having output terminals coupled to a differential output. A transmission controller is configured to transmit data into the main and compensation data paths, the data corresponding to pairs of sequentially transmitted bits including an odd data bit followed by an even data bit, and further configured to determine respective duty cycle widths for each of the odd and even data bits as received by the transmission controller. The transmission controller is configured to cause the first and second driver circuits to equalize the respective duty cycle widths of the odd and even data bits, as transmitted, based their respective duty cycle widths as received.

Abstract translation: 公开了一种用于占空比失真补偿的方法和装置。 在一个实施例中，集成电路包括具有主数据路径和补偿数据路径的差分信号发送器。 主数据路径包括具有耦合到差分输出的输出端的第一和第二差分驱动器电路。 发送控制器被配置为将数据发送到主和补偿数据路径中，数据对应于顺序发送的比特对，包括奇数数据位，后跟偶数数据位，并进一步被配置为确定各个占空比宽度 由传输控制器接收的奇数和偶数数据位。 传输控制器被配置为使得第一和第二驱动器电路基于其所接收的各自的占空比宽度来均衡发送的奇数和偶数数据位的相应占空比宽度。