公开(公告)号：US08994427B2

公开(公告)日：2015-03-31

申请号：US13937424

申请日：2013-07-09

Applicant: Oracle International Corporation

Inventor： Zuxu Qin ,  Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Baoqing Huang ,  Yan Yan

IPC: H03K7/08

CPC classification number: H03K7/08 ,  H03K5/1565

Abstract: A method and apparatus for duty cycle distortion compensation is disclosed. In one embodiment, an integrated circuit includes a differential signal transmitter having a main data path and a compensation data path. The main data path includes a first and second differential driver circuits each having output terminals coupled to a differential output. A transmission controller is configured to transmit data into the main and compensation data paths, the data corresponding to pairs of sequentially transmitted bits including an odd data bit followed by an even data bit, and further configured to determine respective duty cycle widths for each of the odd and even data bits as received by the transmission controller. The transmission controller is configured to cause the first and second driver circuits to equalize the respective duty cycle widths of the odd and even data bits, as transmitted, based their respective duty cycle widths as received.

Abstract translation: 公开了一种用于占空比失真补偿的方法和装置。 在一个实施例中，集成电路包括具有主数据路径和补偿数据路径的差分信号发送器。 主数据路径包括具有耦合到差分输出的输出端的第一和第二差分驱动器电路。 发送控制器被配置为将数据发送到主和补偿数据路径中，数据对应于顺序发送的比特对，包括奇数数据位，后跟偶数数据位，并进一步被配置为确定各个占空比宽度 由传输控制器接收的奇数和偶数数据位。 传输控制器被配置为使得第一和第二驱动器电路基于其所接收的各自的占空比宽度来均衡发送的奇数和偶数数据位的相应占空比宽度。

公开(公告)号：US20150015315A1

公开(公告)日：2015-01-15

申请号：US13937424

申请日：2013-07-09

Applicant: Oracle International Corporation

Inventor： Zuxu Qin ,  Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Baoqing Huang ,  Yan Yan

IPC: H03K7/08

CPC classification number: H03K7/08 ,  H03K5/1565

Abstract: A method and apparatus for duty cycle distortion compensation is disclosed. In one embodiment, an integrated circuit includes a differential signal transmitter having a main data path and a compensation data path. The main data path includes a first and second differential driver circuits each having output terminals coupled to a differential output. A transmission controller is configured to transmit data into the main and compensation data paths, the data corresponding to pairs of sequentially transmitted bits including an odd data bit followed by an even data bit, and further configured to determine respective duty cycle widths for each of the odd and even data bits as received by the transmission controller. The transmission controller is configured to cause the first and second driver circuits to equalize the respective duty cycle widths of the odd and even data bits, as transmitted, based their respective duty cycle widths as received.

Abstract translation: 公开了一种用于占空比失真补偿的方法和装置。 在一个实施例中，集成电路包括具有主数据路径和补偿数据路径的差分信号发送器。 主数据路径包括具有耦合到差分输出的输出端的第一和第二差分驱动器电路。 发送控制器被配置为将数据发送到主和补偿数据路径中，数据对应于顺序发送的比特对，包括奇数数据位，后跟偶数数据位，并进一步被配置为确定各个占空比宽度 由传输控制器接收的奇数和偶数数据位。 传输控制器被配置为使得第一和第二驱动器电路基于其所接收的各自的占空比宽度来均衡发送的奇数和偶数数据位的相应占空比宽度。

公开(公告)号：US09306732B2

公开(公告)日：2016-04-05

申请号：US14146605

申请日：2014-01-02

Applicant: Oracle International Corporation

Inventor： Dawei Huang ,  Jianghui Su ,  Hongtao Zhang ,  Deqiang Song

IPC: H04L7/00 ,  H04L7/02 ,  H04L7/033

CPC classification number: H04L7/0087 ,  H04L7/02 ,  H04L7/0334

Abstract: Embodiments include systems and methods for applying a controllable early/late offset to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a serializer/deserializer (SERDES). For example, slope asymmetry around the first precursor of the channel pulse response for the SERDES can tend to skew at-rate CDR determinations of whether to advance or retard clocking. Accordingly, embodiments use asymmetric voting thresholds for generating each of the advance and retard signals in an attempt to de-skew the voting results and effectively tune the CDR to a position either earlier or later than the first precursor zero crossing (i.e., h(−1)=0) position. This can improve link margin and data recovery, particularly for long data channels and/or at higher data rates.

Abstract translation: 实施例包括将可控早/迟补偿应用于速率时钟数据恢复（CDR）系统的系统和方法。 一些实施例在串行器/解串器（SERDES）的CDR电路的上下文中操作。 例如，针对SERDES的信道脉冲响应的第一前体周围的斜率不对称倾向于偏移速率CDR确定是否提前或延迟时钟。 因此，实施例使用非对称投票阈值来产生提前和延迟信号中的每一个，以试图使投票结果去偏移，并有效地将CDR调谐到比第一前体过零点更早或更晚的位置（即h（ - 1）= 0）位置。 这可以改善链路余量和数据恢复，特别是对于长数据信道和/或更高的数据速率。