公开(公告)号：US20190104088A1

公开(公告)日：2019-04-04

申请号：US15722349

申请日：2017-10-02

Applicant: Oracle International Corporation

Inventor： Zuxu Qin ,  Baoqing Huang ,  Dawei Huang ,  Kuai Yin ,  Maoqing Yao ,  Philip Kwan

IPC: H04L12/935 ,  H04L9/06 ,  B23P19/04

Abstract: Embodiments include systems and methods for transmitting data over high-speed data channels in context of serializer/deserializer circuits. Some embodiments include a novel full-rate source-series-terminated (SST) transmitter driver architecture with output charge sharing isolation. Certain implementations have a programmable floating tap (e.g., in addition to standard taps) with both positive and negative FIR values and cursor reduction, which can help achieve large FIR range and high channel equalization capability. Some embodiments operate with multi-phase clocking having phased clock error correction, which can facilitate operation with low-jitter and low-DCD clocks. Some implementations also include novel output inductor structures that are disposed to partially overlap output interface bumps.

公开(公告)号：US10257121B1

公开(公告)日：2019-04-09

申请号：US15722349

申请日：2017-10-02

Applicant: Oracle International Corporation

Inventor： Zuxu Qin ,  Baoqing Huang ,  Dawei Huang ,  Kuai Yin ,  Maoqing Yao ,  Philip Kwan

IPC: H04L9/06 ,  B23P19/04 ,  H04L12/935

Abstract: Embodiments include systems and methods for transmitting data over high-speed data channels in context of serializer/deserializer circuits. Some embodiments include a novel full-rate source-series-terminated (SST) transmitter driver architecture with output charge sharing isolation. Certain implementations have a programmable floating tap (e.g., in addition to standard taps) with both positive and negative FIR values and cursor reduction, which can help achieve large FIR range and high channel equalization capability. Some embodiments operate with multi-phase clocking having phased clock error correction, which can facilitate operation with low-jitter and low-DCD clocks. Some implementations also include novel output inductor structures that are disposed to partially overlap output interface bumps.