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公开(公告)号：US11240073B2
公开(公告)日：2022-02-01
申请号：US16671146
申请日：2019-10-31
Applicant: Oracle International Corporation
Inventor： Xun Zhang , Chaitanya Palusa , Dawei Huang , Muthukumar Vairavan , Jianghui Su
Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, to generate multiple samples for a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.
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公开(公告)号：US11558223B2
公开(公告)日：2023-01-17
申请号：US17648899
申请日：2022-01-25
Applicant: Oracle International Corporation
Inventor： Xun Zhang , Chaitanya Palusa , Dawei Huang , Muthukumar Vairavan , Jianghui Su
Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.
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公开(公告)号：US20180278405A1
公开(公告)日：2018-09-27
申请号：US15466469
申请日：2017-03-22
Applicant: Oracle International Corporation
Inventor： Yuhan Yao , Xun Zhang , Dawei Huang , Jianghui Su , Muthukumar Vairavan , Chaitanya Palusa
CPC classification number: H04L7/0008 , H03L7/0807 , H04B1/16 , H04L7/02
Abstract: Embodiments include systems and methods for improving link performance and tracking capability of a baud-rate clock data recovery (CDR) system using transition pattern detection. For example, a multi-level signal is received via a data channel and converted to a pseudo-NRZ signal. CDR early/late voting can be derived from the converted (baud-rate) pseudo-NRZ signal and from error signals from the received PAM4 signal, and the voting can be implemented with different phase error detector (PED) functional approaches. Different approaches can yield different CDR performance characteristics and can tend to favor different PAM4 transition patterns. Embodiments can identify jittery patterns for a particular CDR implementation and can add features to the CDR to filter out those patterns from being used for CDR early/late voting.
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公开(公告)号：US11784855B2
公开(公告)日：2023-10-10
申请号：US18154248
申请日：2023-01-13
Applicant: Oracle International Corporation
Inventor： Xun Zhang , Chaitanya Palusa , Dawei Huang , Muthukumar Vairavan , Jianghui Su
CPC classification number: H04L25/03057 , H04B1/16
Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.
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公开(公告)号：US20220191071A1
公开(公告)日：2022-06-16
申请号：US17648899
申请日：2022-01-25
Applicant: Oracle International Corporation
Inventor： Xun Zhang , Chaitanya Palusa , Dawei Huang , Muthukumar Vairavan , Jianghui Su
Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.
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Patent Agency Ranking
公开(公告)号：US10135643B1
公开(公告)日：2018-11-20
申请号：US15655034
申请日：2017-07-20
Applicant: Oracle International Corporation
Inventor： Long Kong , Ranjan Vaish , Muthukumar Vairavan , Zuxu Qin
Abstract: An embodiment includes a first feedback tap, a second feedback tap, and a summation circuit. The summation circuit may include a first load and a second load coupled to each other at an internal circuit node, and coupled in series between a power supply node and an output node. The summation circuit may be configured to receive, via a serial communication link, an input signal indicative of a series of data symbols, and to generate an output voltage level on the output node based upon a current data symbol. The first feedback tap, coupled to the output node, may be configured to sink a first current from the output node based upon a first previously received data symbol. The second feedback tap, coupled to an intermediate circuit node, may be configured to sink a second current from the intermediate circuit node based upon a second previously received data symbol.
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公开(公告)号：US20230155867A1
公开(公告)日：2023-05-18
申请号：US18154248
申请日：2023-01-13
Applicant: Oracle International Corporation
Inventor： Xun Zhang , Chaitanya Palusa , Dawei Huang , Muthukumar Vairavan , Jianghui Su
CPC classification number: H04L25/03057 , H04B1/16
Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.
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公开(公告)号：US20210135907A1
公开(公告)日：2021-05-06
申请号：US16671146
申请日：2019-10-31
Applicant: Oracle International Corporation
Inventor： Xun Zhang , Chaitanya Palusa , Dawei Huang , Muthukumar Vairavan , Jianghui Su
Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, to generate multiple samples for a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.
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公开(公告)号：US10483952B1
公开(公告)日：2019-11-19
申请号：US15971126
申请日：2018-05-04
Applicant: Oracle International Corporation
Inventor： Jianghui Su , Xun Zhang , Muthukumar Vairavan , Rajesh Kumar , Dawei Huang
Abstract: A method and an apparatus for correcting baseline wander is disclosed. The method and apparatus may include receiving a serial data stream that encodes a plurality of data symbols, and determining an average magnitude of a first data value included in one or more data symbols of a subset of the plurality of data symbols, and an average magnitude of a second value included in the one of more data symbols of the subset of the plurality of data symbols. A common mode operating point of an equalizer circuit may be adjusted using the average magnitude of the first data value and the average magnitude of the second data value.
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公开(公告)号：US20190341914A1
公开(公告)日：2019-11-07
申请号：US15971126
申请日：2018-05-04
Applicant: Oracle International Corporation
Inventor： Jianghui Su , Xun Zhang , Muthukumar Vairavan , Rajesh Kumar , Dawei Huang
Abstract: A method and an apparatus for correcting baseline wander is disclosed. The method and apparatus may include receiving a serial data stream that encodes a plurality of data symbols, and determining an average magnitude of a first data value included in one or more data symbols of a subset of the plurality of data symbols, and an average magnitude of a second value included in the one of more data symbols of the subset of the plurality of data symbols. A common mode operating point of an equalizer circuit may be adjusted using the average magnitude of the first data value and the average magnitude of the second data value.
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