公开(公告)号：US09806918B1

公开(公告)日：2017-10-31

申请号：US15181167

申请日：2016-06-13

Applicant: Oracle International Corporation

Inventor： Jianghui Su ,  Rajesh Kumar ,  Ranjan Vaish

IPC: H04L25/03 ,  H04L25/02 ,  H04B1/16

CPC classification number: H04L25/03146 ,  H04L25/028 ,  H04L25/03343

Abstract: Embodiments include systems and methods for providing fast direct feedback to correct decision feedback equalization (DFE) in receiver circuits. Embodiments can provide direct feedback for DFE correction in a manner that is effective in high-speed data channels, while manifesting less latency, power consumption, and/or area than conventional DFE implementations. In some implementations, in each clock cycle (e.g., Tn), implementations can select (e.g., using a multiplexer) between a positive reference signal and a negative reference signal (e.g., both reference signals generated according to an inter-symbol interference magnitude for a data channel) according to a decision feedback signal from a previous clock cycle (Tn−1). The selected reference signal can be compared (e.g., in the same clock cycle Tn, using a comparator) with an input data signal to generated an updated decision feedback signal for a next clock cycle (e.g., Tn+1).

公开(公告)号：US10135643B1

公开(公告)日：2018-11-20

申请号：US15655034

申请日：2017-07-20

Applicant: Oracle International Corporation

Inventor： Long Kong ,  Ranjan Vaish ,  Muthukumar Vairavan ,  Zuxu Qin

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04L25/03

Abstract: An embodiment includes a first feedback tap, a second feedback tap, and a summation circuit. The summation circuit may include a first load and a second load coupled to each other at an internal circuit node, and coupled in series between a power supply node and an output node. The summation circuit may be configured to receive, via a serial communication link, an input signal indicative of a series of data symbols, and to generate an output voltage level on the output node based upon a current data symbol. The first feedback tap, coupled to the output node, may be configured to sink a first current from the output node based upon a first previously received data symbol. The second feedback tap, coupled to an intermediate circuit node, may be configured to sink a second current from the intermediate circuit node based upon a second previously received data symbol.