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    Baseline wander correction gain adaptation
    1.
    发明授权
    Baseline wander correction gain adaptation 有权

    公开(公告)号：US09917607B1

    公开(公告)日：2018-03-13

    申请号：US15449619

    申请日：2017-03-03

    Applicant: Oracle International Corporation

    Inventor： Xun Zhang ,  Dawei Huang ,  Jianghui Su ,  Chaitanya Palusa

    IPC: H04L25/03 ,  H04B1/16 ,  H03G3/30 ,  H03M1/66

    CPC classification number: H04B1/16 ,  H03G3/3078 ,  H03G2201/706 ,  H03M1/66 ,  H04L25/03057

    Abstract: Embodiments include systems and methods for baseline wander correction gain adaptation in receiver circuits. Some embodiments operate in context of an alternating current coupled transceiver communicating data signals over a high-speed transmission channel, such that the receiver system includes an AC-coupled data input and a feedback loop with a data slicer and an error slicer. A baseline wander correction (BWC) circuit can be part of the feedback loop and can generate a feedback signal corresponding to low-pass-filtered bits data from the data slicer output and having a gain generated according to pattern-filtered error data from the error slicer output. For example, gain adaptation is performed according to error information corresponding to a detected relatively high-frequency data pattern following a long low-frequency pattern.

    Clock data recovery with increased frequency offset tracking
    2.
    发明授权
    Clock data recovery with increased frequency offset tracking 有权
    时钟数据恢复增加了频率偏移跟踪

    公开(公告)号：US09231752B1

    公开(公告)日：2016-01-05

    申请号：US14639886

    申请日：2015-03-05

    Applicant: ORACLE INTERNATIONAL CORPORATION

    Inventor： Yan Yan ,  Ali Gokhan Ileri ,  Jianghui Su ,  Dawei Huang ,  Xun Zhang ,  Sifang You

    IPC: H04L7/00 ,  H04L7/06

    CPC classification number: H04L7/0016 ,  H03L7/0807 ,  H03L7/0814 ,  H04L7/0062 ,  H04L7/033

    Abstract: Embodiments include systems and methods for increasing frequency offset tracking in clock data recovery (CDR) systems. For example, in asynchronous clocking environments, the receiver-side clock frequency can be offset from the transmitter-side clock. While traditional CDR systems can handle some amount of offset, they are typically ineffective at accurately adapting the receiver-side clocking to an optimal data sampling rate when the offset is excessive. Embodiments include a CDR frequency offset adaptation loop that generates an adaptation signal, which can be monitored to detect an adaptation error arising from excessive frequency offset. In response to the detecting, an offset seed can be selected and injected into the frequency offset adaptation loop, thereby reinitializing the frequency offset adaptation loop with a less stressful seed.

    Abstract translation: 实施例包括用于在时钟数据恢复（CDR）系统中增加频率偏移跟踪的系统和方法。 例如，在异步时钟环境中，接收机侧时钟频率可以偏离发射机侧时钟。 虽然传统的CDR系统可以处理一些偏移量，但是当偏移量过大时，它们通常无效地将接收机侧时钟精确地适配到最佳数据采样率。 实施例包括产生自适应信号的CDR频率偏移适配环路，其可以被监视以检测由过多频率偏移引起的适应误差。 响应于检测，可以选择偏移种子并将其注入到频率偏移适配环路中，从而以较小的压力种子重新初始化频率偏移适配环路。

    ADAPTIVE RECEIVER WITH PRE-CURSOR CANCELATION
    3.
    发明公开
    ADAPTIVE RECEIVER WITH PRE-CURSOR CANCELATION 审中-公开

    公开(公告)号：US20230155867A1

    公开(公告)日：2023-05-18

    申请号：US18154248

    申请日：2023-01-13

    Applicant: Oracle International Corporation

    Inventor： Xun Zhang ,  Chaitanya Palusa ,  Dawei Huang ,  Muthukumar Vairavan ,  Jianghui Su

    IPC: H04L25/03 ,  H04B1/16

    CPC classification number: H04L25/03057 ,  H04B1/16

    Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.

    ADPATIVE RECEIVER WITH PRE-CURSOR CANCELATION
    4.
    发明申请
    ADPATIVE RECEIVER WITH PRE-CURSOR CANCELATION 有权

    公开(公告)号：US20210135907A1

    公开(公告)日：2021-05-06

    申请号：US16671146

    申请日：2019-10-31

    Applicant: Oracle International Corporation

    Inventor： Xun Zhang ,  Chaitanya Palusa ,  Dawei Huang ,  Muthukumar Vairavan ,  Jianghui Su

    IPC: H04L25/03 ,  H04B1/16

    Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, to generate multiple samples for a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.

    Baud-rate clock data recovery with improved tracking performance
    7.
    发明授权
    Baud-rate clock data recovery with improved tracking performance 有权

    公开(公告)号：US10142089B2

    公开(公告)日：2018-11-27

    申请号：US15466469

    申请日：2017-03-22

    Applicant: Oracle International Corporation

    Inventor： Yuhan Yao ,  Xun Zhang ,  Dawei Huang ,  Jianghui Su ,  Muthukumar Vairavan ,  Chaitanya Palusa

    IPC: H04L7/00 ,  H04L7/02 ,  H04B1/16 ,  H03L7/08

    Abstract: Embodiments include systems and methods for improving link performance and tracking capability of a baud-rate clock data recovery (CDR) system using transition pattern detection. For example, a multi-level signal is received via a data channel and converted to a pseudo-NRZ signal. CDR early/late voting can be derived from the converted (baud-rate) pseudo-NRZ signal and from error signals from the received PAM4 signal, and the voting can be implemented with different phase error detector (PED) functional approaches. Different approaches can yield different CDR performance characteristics and can tend to favor different PAM4 transition patterns. Embodiments can identify jittery patterns for a particular CDR implementation and can add features to the CDR to filter out those patterns from being used for CDR early/late voting.

    Adaptive receiver with pre-cursor cancelation
    8.
    发明授权
    Adaptive receiver with pre-cursor cancelation 有权

    公开(公告)号：US11784855B2

    公开(公告)日：2023-10-10

    申请号：US18154248

    申请日：2023-01-13

    Applicant: Oracle International Corporation

    Inventor： Xun Zhang ,  Chaitanya Palusa ,  Dawei Huang ,  Muthukumar Vairavan ,  Jianghui Su

    IPC: H04L25/03 ,  H04B1/16

    CPC classification number: H04L25/03057 ,  H04B1/16

    Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.

    ADAPTIVE RECEIVER WITH PRE-CURSOR CANCELATION
    9.
    发明申请
    ADAPTIVE RECEIVER WITH PRE-CURSOR CANCELATION 有权

    公开(公告)号：US20220191071A1

    公开(公告)日：2022-06-16

    申请号：US17648899

    申请日：2022-01-25

    Applicant: Oracle International Corporation

    Inventor： Xun Zhang ,  Chaitanya Palusa ,  Dawei Huang ,  Muthukumar Vairavan ,  Jianghui Su

    IPC: H04L25/03 ,  H04B1/16

    Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.

    Multi-rate finite impulse response filter
    10.
    发明授权
    Multi-rate finite impulse response filter 有权

    公开(公告)号：US10142134B2

    公开(公告)日：2018-11-27

    申请号：US15456778

    申请日：2017-03-13

    Applicant: Oracle International Corporation

    Inventor： Jiangyuan Li ,  Xun Zhang ,  Jianghui Su

    IPC: H04L12/825 ,  H04L25/03

    Abstract: Embodiments include systems and methods for implementing a multi-rate FIR by using rate-dependent bit stuffing on the cursor, while using rate-independent (e.g., full-rate) spacing on the pre- and post-cursor. For example, in the FIR data path, the cursor bit output is generated using bit stuffing, depending on a selected rate mode (e.g., full-rate, half-rate, quarter-rate, eighth-rate, etc.), but the spacing of the pre-cursor, cursor, and post-cursor are maintained at 1 UI apart (i.e., the full-rate spacing) for all rate modes. Such an approach can appreciably reduce complexity of the logic and can appreciably relieve the critical timing path.

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