公开(公告)号：US09484967B1

公开(公告)日：2016-11-01

申请号：US14681796

申请日：2015-04-08

Applicant: Oracle International Corporation

Inventor： Jianghui Su ,  Yan Yan ,  Jieda Li

IPC: H04L25/08 ,  H04B1/10 ,  H04B17/24 ,  H04B17/21

CPC classification number: H04L25/08 ,  H04B17/21 ,  H04B17/24 ,  H04L25/03114 ,  H04L25/06 ,  H04L25/14

Abstract: An embodiment includes a receiver circuit, a feedback circuit and a control circuit. The receiver circuit is configured to receive each data bit of a plurality of data bits. The feedback circuit is configured to measure a first interference level generated by a first data bit of a first subset of the plurality of data bits on a second data bit of the plurality of data bits to generate one of a first plurality of feedback values. The feedback circuit is also configured to measure a second interference level generated by a third data bit of a second subset of the plurality of data bits on a fourth data bit of the plurality of data bits to generate one of a second plurality of feedback values. The control circuit is configured to determine a duty cycle dependent upon a comparison of the first plurality to the second plurality.

Abstract translation: 实施例包括接收器电路，反馈电路和控制电路。 接收器电路被配置为接收多个数据位的每个数据位。 反馈电路被配置为测量由多个数据位的第二数据位上的多个数据位的第一子集的第一数据位产生的第一干扰电平，以产生第一多个反馈值之一。 反馈电路还被配置为测量由多个数据位的第四数据位上的多个数据位的第二子集的第三数据位产生的第二干扰电平，以产生第二多个反馈值之一。 控制电路被配置为确定取决于第一多个到第二个的比较的占空比。

公开(公告)号：US09141459B2

公开(公告)日：2015-09-22

申请号：US14146904

申请日：2014-01-03

Applicant: Oracle International Corporation

Inventor： Jianghui Su ,  Pu Chuang ,  Yan Yan

IPC: G06F11/00 ,  G06F11/07

CPC classification number: H04L1/205

Abstract: A system may include one or more high-speed serial interfaces for moving data. A system may include a transmission unit configured to serially transmit data bits, and a receiving unit coupled to the transmission unit. The receiving unit may receive a stream of data bits from the transmission unit and establish an initial sample point. The receiving unit may then sample the bits at multiple offsets from the initial sample point, reestablishing the initial sample point between each offset. The receiving unit may also calculate bit error rates (BERs) for the samples taken at each sample point. Based on the BERs, the receiving unit may set a data sampling point for receiving a second stream of data bits from the transmitter unit. The receiving unit may limit the amount of time the data sampling point is used and recalculate the data sampling point when the amount of time has expired.

Abstract translation: 系统可以包括用于移动数据的一个或多个高速串行接口。 系统可以包括被配置为串行发送数据位的传输单元和耦合到传输单元的接收单元。 接收单元可以从传输单元接收数据比特流并建立初始采样点。 然后，接收单元可以从初始采样点以多个偏移采样位，重新建立每个偏移之间的初始采样点。 接收单元还可以计算在每个采样点采集的采样的误码率（BER）。 基于BER，接收单元可以设置用于从发送器单元接收第二数据比特流的数据采样点。 接收单元可以限制使用数据采样点的时间量，并且在时间量过期时重新计算数据采样点。

公开(公告)号：US08994427B2

公开(公告)日：2015-03-31

申请号：US13937424

申请日：2013-07-09

Applicant: Oracle International Corporation

Inventor： Zuxu Qin ,  Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Baoqing Huang ,  Yan Yan

IPC: H03K7/08

CPC classification number: H03K7/08 ,  H03K5/1565

Abstract: A method and apparatus for duty cycle distortion compensation is disclosed. In one embodiment, an integrated circuit includes a differential signal transmitter having a main data path and a compensation data path. The main data path includes a first and second differential driver circuits each having output terminals coupled to a differential output. A transmission controller is configured to transmit data into the main and compensation data paths, the data corresponding to pairs of sequentially transmitted bits including an odd data bit followed by an even data bit, and further configured to determine respective duty cycle widths for each of the odd and even data bits as received by the transmission controller. The transmission controller is configured to cause the first and second driver circuits to equalize the respective duty cycle widths of the odd and even data bits, as transmitted, based their respective duty cycle widths as received.

Abstract translation: 公开了一种用于占空比失真补偿的方法和装置。 在一个实施例中，集成电路包括具有主数据路径和补偿数据路径的差分信号发送器。 主数据路径包括具有耦合到差分输出的输出端的第一和第二差分驱动器电路。 发送控制器被配置为将数据发送到主和补偿数据路径中，数据对应于顺序发送的比特对，包括奇数数据位，后跟偶数数据位，并进一步被配置为确定各个占空比宽度 由传输控制器接收的奇数和偶数数据位。 传输控制器被配置为使得第一和第二驱动器电路基于其所接收的各自的占空比宽度来均衡发送的奇数和偶数数据位的相应占空比宽度。

公开(公告)号：US09231752B1

公开(公告)日：2016-01-05

申请号：US14639886

申请日：2015-03-05

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Yan Yan ,  Ali Gokhan Ileri ,  Jianghui Su ,  Dawei Huang ,  Xun Zhang ,  Sifang You

IPC: H04L7/00 ,  H04L7/06

CPC classification number: H04L7/0016 ,  H03L7/0807 ,  H03L7/0814 ,  H04L7/0062 ,  H04L7/033

Abstract: Embodiments include systems and methods for increasing frequency offset tracking in clock data recovery (CDR) systems. For example, in asynchronous clocking environments, the receiver-side clock frequency can be offset from the transmitter-side clock. While traditional CDR systems can handle some amount of offset, they are typically ineffective at accurately adapting the receiver-side clocking to an optimal data sampling rate when the offset is excessive. Embodiments include a CDR frequency offset adaptation loop that generates an adaptation signal, which can be monitored to detect an adaptation error arising from excessive frequency offset. In response to the detecting, an offset seed can be selected and injected into the frequency offset adaptation loop, thereby reinitializing the frequency offset adaptation loop with a less stressful seed.

Abstract translation: 实施例包括用于在时钟数据恢复（CDR）系统中增加频率偏移跟踪的系统和方法。 例如，在异步时钟环境中，接收机侧时钟频率可以偏离发射机侧时钟。 虽然传统的CDR系统可以处理一些偏移量，但是当偏移量过大时，它们通常无效地将接收机侧时钟精确地适配到最佳数据采样率。 实施例包括产生自适应信号的CDR频率偏移适配环路，其可以被监视以检测由过多频率偏移引起的适应误差。 响应于检测，可以选择偏移种子并将其注入到频率偏移适配环路中，从而以较小的压力种子重新初始化频率偏移适配环路。

公开(公告)号：US20150193288A1

公开(公告)日：2015-07-09

申请号：US14146904

申请日：2014-01-03

Applicant: Oracle International Corporation

Inventor： Jianghui Su ,  Pu Chuang ,  Yan Yan

IPC: G06F11/07

CPC classification number: H04L1/205

Abstract: A system may include one or more high-speed serial interfaces for moving data. A system may include a transmission unit configured to serially transmit data bits, and a receiving unit coupled to the transmission unit. The receiving unit may receive a stream of data bits from the transmission unit and establish an initial sample point. The receiving unit may then sample the bits at multiple offsets from the initial sample point, reestablishing the initial sample point between each offset. The receiving unit may also calculate bit error rates (BERs) for the samples taken at each sample point. Based on the BERs, the receiving unit may set a data sampling point for receiving a second stream of data bits from the transmitter unit. The receiving unit may limit the amount of time the data sampling point is used and recalculate the data sampling point when the amount of time has expired.

Abstract translation: 系统可以包括用于移动数据的一个或多个高速串行接口。 系统可以包括被配置为串行发送数据位的传输单元和耦合到传输单元的接收单元。 接收单元可以从传输单元接收数据比特流并建立初始采样点。 然后，接收单元可以从初始采样点以多个偏移采样位，重新建立每个偏移之间的初始采样点。 接收单元还可以计算在每个采样点采集的采样的误码率（BER）。 基于BER，接收单元可以设置用于从发送器单元接收第二数据比特流的数据采样点。 接收单元可以限制使用数据采样点的时间量，并且在时间量过期时重新计算数据采样点。

公开(公告)号：US20160301435A1

公开(公告)日：2016-10-13

申请号：US14681796

申请日：2015-04-08

Applicant: Oracle International Corporation

Inventor： Jianghui Su ,  Yan Yan ,  Jieda Li

IPC: H04B1/10 ,  H04B17/21 ,  H04B17/24

CPC classification number: H04L25/08 ,  H04B17/21 ,  H04B17/24 ,  H04L25/03114 ,  H04L25/06 ,  H04L25/14

Abstract: An embodiment includes a receiver circuit, a feedback circuit and a control circuit. The receiver circuit is configured to receive each data bit of a plurality of data bits. The feedback circuit is configured to measure a first interference level generated by a first data bit of a first subset of the plurality of data bits on a second data bit of the plurality of data bits to generate one of a first plurality of feedback values. The feedback circuit is also configured to measure a second interference level generated by a third data bit of a second subset of the plurality of data bits on a fourth data bit of the plurality of data bits to generate one of a second plurality of feedback values. The control circuit is configured to determine a duty cycle dependent upon a comparison of the first plurality to the second plurality.

Abstract translation: 实施例包括接收器电路，反馈电路和控制电路。 接收器电路被配置为接收多个数据位的每个数据位。 反馈电路被配置为测量由多个数据位的第二数据位上的多个数据位的第一子集的第一数据位产生的第一干扰电平，以产生第一多个反馈值之一。 反馈电路还被配置为测量由多个数据位的第四数据位上的多个数据位的第二子集的第三数据位产生的第二干扰电平，以产生第二多个反馈值之一。 控制电路被配置为确定取决于第一多个到第二个的比较的占空比。

公开(公告)号：US20150015315A1

公开(公告)日：2015-01-15

申请号：US13937424

申请日：2013-07-09

Applicant: Oracle International Corporation

Inventor： Zuxu Qin ,  Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Baoqing Huang ,  Yan Yan

IPC: H03K7/08

CPC classification number: H03K7/08 ,  H03K5/1565

Abstract: A method and apparatus for duty cycle distortion compensation is disclosed. In one embodiment, an integrated circuit includes a differential signal transmitter having a main data path and a compensation data path. The main data path includes a first and second differential driver circuits each having output terminals coupled to a differential output. A transmission controller is configured to transmit data into the main and compensation data paths, the data corresponding to pairs of sequentially transmitted bits including an odd data bit followed by an even data bit, and further configured to determine respective duty cycle widths for each of the odd and even data bits as received by the transmission controller. The transmission controller is configured to cause the first and second driver circuits to equalize the respective duty cycle widths of the odd and even data bits, as transmitted, based their respective duty cycle widths as received.

Abstract translation: 公开了一种用于占空比失真补偿的方法和装置。 在一个实施例中，集成电路包括具有主数据路径和补偿数据路径的差分信号发送器。 主数据路径包括具有耦合到差分输出的输出端的第一和第二差分驱动器电路。 发送控制器被配置为将数据发送到主和补偿数据路径中，数据对应于顺序发送的比特对，包括奇数数据位，后跟偶数数据位，并进一步被配置为确定各个占空比宽度 由传输控制器接收的奇数和偶数数据位。 传输控制器被配置为使得第一和第二驱动器电路基于其所接收的各自的占空比宽度来均衡发送的奇数和偶数数据位的相应占空比宽度。