公开(公告)号：US09917607B1

公开(公告)日：2018-03-13

申请号：US15449619

申请日：2017-03-03

Applicant: Oracle International Corporation

Inventor： Xun Zhang ,  Dawei Huang ,  Jianghui Su ,  Chaitanya Palusa

IPC: H04L25/03 ,  H04B1/16 ,  H03G3/30 ,  H03M1/66

CPC classification number: H04B1/16 ,  H03G3/3078 ,  H03G2201/706 ,  H03M1/66 ,  H04L25/03057

Abstract: Embodiments include systems and methods for baseline wander correction gain adaptation in receiver circuits. Some embodiments operate in context of an alternating current coupled transceiver communicating data signals over a high-speed transmission channel, such that the receiver system includes an AC-coupled data input and a feedback loop with a data slicer and an error slicer. A baseline wander correction (BWC) circuit can be part of the feedback loop and can generate a feedback signal corresponding to low-pass-filtered bits data from the data slicer output and having a gain generated according to pattern-filtered error data from the error slicer output. For example, gain adaptation is performed according to error information corresponding to a detected relatively high-frequency data pattern following a long low-frequency pattern.

公开(公告)号：US09231752B1

公开(公告)日：2016-01-05

申请号：US14639886

申请日：2015-03-05

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Yan Yan ,  Ali Gokhan Ileri ,  Jianghui Su ,  Dawei Huang ,  Xun Zhang ,  Sifang You

IPC: H04L7/00 ,  H04L7/06

CPC classification number: H04L7/0016 ,  H03L7/0807 ,  H03L7/0814 ,  H04L7/0062 ,  H04L7/033

Abstract: Embodiments include systems and methods for increasing frequency offset tracking in clock data recovery (CDR) systems. For example, in asynchronous clocking environments, the receiver-side clock frequency can be offset from the transmitter-side clock. While traditional CDR systems can handle some amount of offset, they are typically ineffective at accurately adapting the receiver-side clocking to an optimal data sampling rate when the offset is excessive. Embodiments include a CDR frequency offset adaptation loop that generates an adaptation signal, which can be monitored to detect an adaptation error arising from excessive frequency offset. In response to the detecting, an offset seed can be selected and injected into the frequency offset adaptation loop, thereby reinitializing the frequency offset adaptation loop with a less stressful seed.

Abstract translation: 实施例包括用于在时钟数据恢复（CDR）系统中增加频率偏移跟踪的系统和方法。 例如，在异步时钟环境中，接收机侧时钟频率可以偏离发射机侧时钟。 虽然传统的CDR系统可以处理一些偏移量，但是当偏移量过大时，它们通常无效地将接收机侧时钟精确地适配到最佳数据采样率。 实施例包括产生自适应信号的CDR频率偏移适配环路，其可以被监视以检测由过多频率偏移引起的适应误差。 响应于检测，可以选择偏移种子并将其注入到频率偏移适配环路中，从而以较小的压力种子重新初始化频率偏移适配环路。

公开(公告)号：US09184906B1

公开(公告)日：2015-11-10

申请号：US14492420

申请日：2014-09-22

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Jihong Min ,  Dawei Huang ,  Jianghui Su ,  Hongtao Zhang

IPC: H04L7/00

CPC classification number: H04L7/0334 ,  H04L7/0016 ,  H04L7/0062 ,  H04L7/0087

Abstract: Embodiments include systems and methods for using generalized pulse amplitude modulation (PAM-X) signaling with an at-rate not-return-to-zero (NRZ) clock data recovery (CDR) system. Some implementations include dual-mode signaling for an at-rate CDR (e.g., using standard NRZ signaling at lower operating frequencies and pseudo-NRZ signaling derived from PAM-X signaling at higher operating frequencies. Embodiments derive an apparent direction of signal transition from PAM-X signaling. The direction can be used to calculate pseudo-NRZ values. For example, when the PAM-X signal transitions in an upward direction, a pseudo-current NRZ value and a pseudo-previous NRZ value of ‘−1’ and ‘+1’ can be generated, respectively. An at-rate NRZ CDR can use the pseudo-NRZ values and a derived error value to make an offset determination. The offset determination can then be used to offset a generated clock signal in the CDR system.

Abstract translation: 实施例包括用于使用通率不归零（NRZ）时钟数据恢复（CDR）系统的广义脉冲幅度调制（PAM-X）信令的系统和方法。 一些实现方案包括用于速率CDR的双模式信令（例如，在较低工作频率下使用标准NRZ信令和在较高工作频率下从PAM-X信令导出的伪NRZ信令。实施例导出来自PAM的信号转换的明显方向 -X信号，该方向可用于计算伪NRZ值，例如，当PAM-X信号向上转换时，伪电流NRZ值和伪前NRZ值为“-1”， 可以分别产生'+1'，高速NRZ CDR可以使用伪NRZ值和派生误差值进行偏移确定，然后可以使用偏移确定来补偿CDR中产生的时钟信号 系统。

公开(公告)号：US20150193288A1

公开(公告)日：2015-07-09

申请号：US14146904

申请日：2014-01-03

Applicant: Oracle International Corporation

Inventor： Jianghui Su ,  Pu Chuang ,  Yan Yan

IPC: G06F11/07

CPC classification number: H04L1/205

Abstract: A system may include one or more high-speed serial interfaces for moving data. A system may include a transmission unit configured to serially transmit data bits, and a receiving unit coupled to the transmission unit. The receiving unit may receive a stream of data bits from the transmission unit and establish an initial sample point. The receiving unit may then sample the bits at multiple offsets from the initial sample point, reestablishing the initial sample point between each offset. The receiving unit may also calculate bit error rates (BERs) for the samples taken at each sample point. Based on the BERs, the receiving unit may set a data sampling point for receiving a second stream of data bits from the transmitter unit. The receiving unit may limit the amount of time the data sampling point is used and recalculate the data sampling point when the amount of time has expired.

Abstract translation: 系统可以包括用于移动数据的一个或多个高速串行接口。 系统可以包括被配置为串行发送数据位的传输单元和耦合到传输单元的接收单元。 接收单元可以从传输单元接收数据比特流并建立初始采样点。 然后，接收单元可以从初始采样点以多个偏移采样位，重新建立每个偏移之间的初始采样点。 接收单元还可以计算在每个采样点采集的采样的误码率（BER）。 基于BER，接收单元可以设置用于从发送器单元接收第二数据比特流的数据采样点。 接收单元可以限制使用数据采样点的时间量，并且在时间量过期时重新计算数据采样点。

公开(公告)号：US09031179B2

公开(公告)日：2015-05-12

申请号：US13936961

申请日：2013-07-08

Applicant: Oracle International Corporation

Inventor： Jianghui Su

IPC: H04L7/00 ,  H04B17/00

CPC classification number: H04L7/0087 ,  H04B17/11 ,  H04L7/0037 ,  H04L7/0041 ,  H04L7/033

Abstract: Embodiments include systems and methods for calibrating effective clock path mismatches in a receiver circuit. For example, a serializer/deserializer (SERDES) circuit includes a data slicer that generates data sampler decisions by sampling an input signal according to a clocking signal, and an error slicer that generates error slicer samples by sampling the input signal according to the clocking signal. Each of the data slicer and error slicer has an associated clock path delay, and the delays are typically different (e.g., due to manufacturing differences). A calibrator performs iteratively shifted sampling and comparing of the data sampler decisions and the error slicer samples over a plurality of clocking locations to determine an effective clock path mismatch. The calibrator can then determine and apply a clocking offset to the data slicer and/or the error slicer to effectively shift data and error sampling, thereby compensating for the effective clock path mismatch.

Abstract translation: 实施例包括用于校准接收机电路中的有效时钟路径不匹配的系统和方法。 例如，串行器/解串器（SERDES）电路包括通过根据时钟信号对输入信号进行采样来生成数据采样器判定的数据限幅器，以及通过根据时钟信号对输入信号进行采样来产生误差限幅器采样的误差限幅器 。 每个数据限幅器和误差限幅器具有相关联的时钟路径延迟，并且延迟通常是不同的（例如，由于制造差异）。 校准器在多个时钟位置执行迭代移位采样和比较数据采样器判决和误差限幅器采样以确定有效的时钟路径失配。 然后，校准器可以确定并应用时钟偏移到数据限幅器和/或误差限幅器，以有效地移位数据和误差采样，从而补偿有效时钟路径失配。

公开(公告)号：US11558223B2

公开(公告)日：2023-01-17

申请号：US17648899

申请日：2022-01-25

Applicant: Oracle International Corporation

Inventor： Xun Zhang ,  Chaitanya Palusa ,  Dawei Huang ,  Muthukumar Vairavan ,  Jianghui Su

IPC: H04L25/03 ,  H04B1/16

Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.

公开(公告)号：US20180278405A1

公开(公告)日：2018-09-27

申请号：US15466469

申请日：2017-03-22

Applicant: Oracle International Corporation

Inventor： Yuhan Yao ,  Xun Zhang ,  Dawei Huang ,  Jianghui Su ,  Muthukumar Vairavan ,  Chaitanya Palusa

IPC: H04L7/00 ,  H04L7/02 ,  H04B1/16 ,  H03L7/08

CPC classification number: H04L7/0008 ,  H03L7/0807 ,  H04B1/16 ,  H04L7/02

Abstract: Embodiments include systems and methods for improving link performance and tracking capability of a baud-rate clock data recovery (CDR) system using transition pattern detection. For example, a multi-level signal is received via a data channel and converted to a pseudo-NRZ signal. CDR early/late voting can be derived from the converted (baud-rate) pseudo-NRZ signal and from error signals from the received PAM4 signal, and the voting can be implemented with different phase error detector (PED) functional approaches. Different approaches can yield different CDR performance characteristics and can tend to favor different PAM4 transition patterns. Embodiments can identify jittery patterns for a particular CDR implementation and can add features to the CDR to filter out those patterns from being used for CDR early/late voting.

公开(公告)号：US20150015315A1

公开(公告)日：2015-01-15

申请号：US13937424

申请日：2013-07-09

Applicant: Oracle International Corporation

Inventor： Zuxu Qin ,  Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Baoqing Huang ,  Yan Yan

IPC: H03K7/08

CPC classification number: H03K7/08 ,  H03K5/1565

Abstract: A method and apparatus for duty cycle distortion compensation is disclosed. In one embodiment, an integrated circuit includes a differential signal transmitter having a main data path and a compensation data path. The main data path includes a first and second differential driver circuits each having output terminals coupled to a differential output. A transmission controller is configured to transmit data into the main and compensation data paths, the data corresponding to pairs of sequentially transmitted bits including an odd data bit followed by an even data bit, and further configured to determine respective duty cycle widths for each of the odd and even data bits as received by the transmission controller. The transmission controller is configured to cause the first and second driver circuits to equalize the respective duty cycle widths of the odd and even data bits, as transmitted, based their respective duty cycle widths as received.

Abstract translation: 公开了一种用于占空比失真补偿的方法和装置。 在一个实施例中，集成电路包括具有主数据路径和补偿数据路径的差分信号发送器。 主数据路径包括具有耦合到差分输出的输出端的第一和第二差分驱动器电路。 发送控制器被配置为将数据发送到主和补偿数据路径中，数据对应于顺序发送的比特对，包括奇数数据位，后跟偶数数据位，并进一步被配置为确定各个占空比宽度 由传输控制器接收的奇数和偶数数据位。 传输控制器被配置为使得第一和第二驱动器电路基于其所接收的各自的占空比宽度来均衡发送的奇数和偶数数据位的相应占空比宽度。

公开(公告)号：US11240073B2

公开(公告)日：2022-02-01

申请号：US16671146

申请日：2019-10-31

Applicant: Oracle International Corporation

Inventor： Xun Zhang ,  Chaitanya Palusa ,  Dawei Huang ,  Muthukumar Vairavan ,  Jianghui Su

IPC: H04L25/03 ,  H04B1/16

Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, to generate multiple samples for a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.

公开(公告)号：US09813227B2

公开(公告)日：2017-11-07

申请号：US15000028

申请日：2016-01-18

Applicant: Oracle International Corporation

Inventor： Jianghui Su

IPC: H04L7/00 ,  H04L7/02 ,  H04L7/033

CPC classification number: H04L7/0087 ,  H04L7/0033 ,  H04L7/02 ,  H04L7/0334

Abstract: Embodiments include systems and methods for applying a controllable early/late offset to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a serializer/deserializer (SERDES). For example, slope asymmetry around the first precursor of the channel pulse response for the SERDES can tend to skew at-rate CDR determinations of whether to advance or retard clocking. Accordingly, embodiments use asymmetric voting thresholds for generating each of the advance and retard signals in an attempt to de-skew the voting results and effectively tune the CDR to a position either earlier or later than the first precursor zero crossing (i.e., h(−1)=0) position. This can improve link margin and data recovery, particularly for long data channels and/or at higher data rates.