公开(公告)号：US20140215245A1

公开(公告)日：2014-07-31

申请号：US13753130

申请日：2013-01-29

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Hongtao Zhang ,  Da-wei Huang ,  Jianghui Su

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  H04L12/6418

Abstract: Systems and methods for reducing power consumption of systems using serialized data transmission. In a multi-node system, the reiterative steps for the setup of the lanes within links between the nodes produces both a time invariant set of parameters associated with the channel properties of the lanes and a time variant set of parameters associated with receiver clock alignment. The time invariant set is stored in persistent storage. Links may be turned on and turned off. When a link is turned on again, the stored time invariant set may be used as initial values to reconfigure both the time invariant and the time variant sets, thereby greatly reducing the delay to begin using the link again. The reduced delay may significantly speed up the wakening process for the links, thereby encouraging the use of low-power techniques that include tuning off lanes.

Abstract translation: 使用串行数据传输降低系统功耗的系统和方法。 在多节点系统中，用于在节点之间的链路内建立通道的重复步骤产生与通道的通道属性相关联的时间不变量参数和与接收器时钟对准相关联的参数的时变集合。 时间不变集存储在持久存储器中。 链接可能会打开并关闭。 当再次打开链接时，可以将所存储的时间不变集合用作初始值以重新配置时间不变集合和时间变量集合，从而大大减少开始再次使用链接的延迟。 减少的延迟可能会显着加速链路的唤醒过程，从而鼓励使用包括调整车道的低功率技术。

公开(公告)号：US09306732B2

公开(公告)日：2016-04-05

申请号：US14146605

申请日：2014-01-02

Applicant: Oracle International Corporation

Inventor： Dawei Huang ,  Jianghui Su ,  Hongtao Zhang ,  Deqiang Song

IPC: H04L7/00 ,  H04L7/02 ,  H04L7/033

CPC classification number: H04L7/0087 ,  H04L7/02 ,  H04L7/0334

Abstract: Embodiments include systems and methods for applying a controllable early/late offset to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a serializer/deserializer (SERDES). For example, slope asymmetry around the first precursor of the channel pulse response for the SERDES can tend to skew at-rate CDR determinations of whether to advance or retard clocking. Accordingly, embodiments use asymmetric voting thresholds for generating each of the advance and retard signals in an attempt to de-skew the voting results and effectively tune the CDR to a position either earlier or later than the first precursor zero crossing (i.e., h(−1)=0) position. This can improve link margin and data recovery, particularly for long data channels and/or at higher data rates.

Abstract translation: 实施例包括将可控早/迟补偿应用于速率时钟数据恢复（CDR）系统的系统和方法。 一些实施例在串行器/解串器（SERDES）的CDR电路的上下文中操作。 例如，针对SERDES的信道脉冲响应的第一前体周围的斜率不对称倾向于偏移速率CDR确定是否提前或延迟时钟。 因此，实施例使用非对称投票阈值来产生提前和延迟信号中的每一个，以试图使投票结果去偏移，并有效地将CDR调谐到比第一前体过零点更早或更晚的位置（即h（ - 1）= 0）位置。 这可以改善链路余量和数据恢复，特别是对于长数据信道和/或更高的数据速率。

公开(公告)号：US09052900B2

公开(公告)日：2015-06-09

申请号：US13753130

申请日：2013-01-29

Applicant: Oracle International Corporation

Inventor： Hongtao Zhang ,  Da-wei Huang ,  Jianghui Su

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  H04L12/6418

Abstract: Systems and methods for reducing power consumption of systems using serialized data transmission. In a multi-node system, the reiterative steps for the setup of the lanes within links between the nodes produces both a time invariant set of parameters associated with the channel properties of the lanes and a time variant set of parameters associated with receiver clock alignment. The time invariant set is stored in persistent storage. Links may be turned on and turned off. When a link is turned on again, the stored time invariant set may be used as initial values to reconfigure both the time invariant and the time variant sets, thereby greatly reducing the delay to begin using the link again. The reduced delay may significantly speed up the wakening process for the links, thereby encouraging the use of low-power techniques that include tuning off lanes.

Abstract translation: 使用串行数据传输降低系统功耗的系统和方法。 在多节点系统中，用于在节点之间的链路内建立通道的重复步骤产生与通道的通道属性相关联的时间不变量参数和与接收器时钟对准相关联的参数的时变集合。 时间不变集存储在持久存储器中。 链接可能会打开并关闭。 当再次打开链接时，可以将所存储的时间不变集合用作初始值以重新配置时间不变集合和时间变量集合，从而大大减少开始再次使用链接的延迟。 减少的延迟可能会显着加速链路的唤醒过程，从而鼓励使用包括调整车道的低功率技术。

公开(公告)号：US09184906B1

公开(公告)日：2015-11-10

申请号：US14492420

申请日：2014-09-22

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Jihong Min ,  Dawei Huang ,  Jianghui Su ,  Hongtao Zhang

IPC: H04L7/00

CPC classification number: H04L7/0334 ,  H04L7/0016 ,  H04L7/0062 ,  H04L7/0087

Abstract: Embodiments include systems and methods for using generalized pulse amplitude modulation (PAM-X) signaling with an at-rate not-return-to-zero (NRZ) clock data recovery (CDR) system. Some implementations include dual-mode signaling for an at-rate CDR (e.g., using standard NRZ signaling at lower operating frequencies and pseudo-NRZ signaling derived from PAM-X signaling at higher operating frequencies. Embodiments derive an apparent direction of signal transition from PAM-X signaling. The direction can be used to calculate pseudo-NRZ values. For example, when the PAM-X signal transitions in an upward direction, a pseudo-current NRZ value and a pseudo-previous NRZ value of ‘−1’ and ‘+1’ can be generated, respectively. An at-rate NRZ CDR can use the pseudo-NRZ values and a derived error value to make an offset determination. The offset determination can then be used to offset a generated clock signal in the CDR system.

Abstract translation: 实施例包括用于使用通率不归零（NRZ）时钟数据恢复（CDR）系统的广义脉冲幅度调制（PAM-X）信令的系统和方法。 一些实现方案包括用于速率CDR的双模式信令（例如，在较低工作频率下使用标准NRZ信令和在较高工作频率下从PAM-X信令导出的伪NRZ信令。实施例导出来自PAM的信号转换的明显方向 -X信号，该方向可用于计算伪NRZ值，例如，当PAM-X信号向上转换时，伪电流NRZ值和伪前NRZ值为“-1”， 可以分别产生'+1'，高速NRZ CDR可以使用伪NRZ值和派生误差值进行偏移确定，然后可以使用偏移确定来补偿CDR中产生的时钟信号 系统。