公开(公告)号：US10142134B2

公开(公告)日：2018-11-27

申请号：US15456778

申请日：2017-03-13

Applicant: Oracle International Corporation

Inventor： Jiangyuan Li ,  Xun Zhang ,  Jianghui Su

IPC: H04L12/825 ,  H04L25/03

Abstract: Embodiments include systems and methods for implementing a multi-rate FIR by using rate-dependent bit stuffing on the cursor, while using rate-independent (e.g., full-rate) spacing on the pre- and post-cursor. For example, in the FIR data path, the cursor bit output is generated using bit stuffing, depending on a selected rate mode (e.g., full-rate, half-rate, quarter-rate, eighth-rate, etc.), but the spacing of the pre-cursor, cursor, and post-cursor are maintained at 1 UI apart (i.e., the full-rate spacing) for all rate modes. Such an approach can appreciably reduce complexity of the logic and can appreciably relieve the critical timing path.

公开(公告)号：US20180278406A1

公开(公告)日：2018-09-27

申请号：US15464972

申请日：2017-03-21

Applicant: Oracle International Corporation

Inventor： Chaitanya Palusa ,  Dawei Huang ,  Jiangyuan Li ,  Pradeep Nagarajan

IPC: H04L7/00

Abstract: Embodiments enable built-in sinusoidal jitter injection, for example, in a serializer/deserializer (SERDES) circuit. For example, embodiments can receive a tracking profile that corresponds to a predetermined sinusoidal jitter (SJ) profile and a predetermined phase interpolator (PI) profile. A shift determination can be made for each of a plurality of insertion times according to the tracking profile, the shift determination indicating whether to adjust phase interpolation of the SERDES circuit. At each of the plurality of insertion times, a phase adjustment signal can be generated as a function of the shift determination. For example, the phase adjustment signal can indicate a control code for a phase interpolator coupled to a clock generator of the SERDES, and the signal can be output to the phase interpolator. Some implementations adjust the phase interpolator in response to the phase adjustment signal, such that the phase interpolator injects SJ that substantially tracks the SJ profile.

公开(公告)号：US10084591B1

公开(公告)日：2018-09-25

申请号：US15464972

申请日：2017-03-21

Applicant: Oracle International Corporation

Inventor： Chaitanya Palusa ,  Dawei Huang ,  Jiangyuan Li ,  Pradeep Nagarajan

IPC: H04L7/00

Abstract: Embodiments enable built-in sinusoidal jitter injection, for example, in a serializer/deserializer (SERDES) circuit. For example, embodiments can receive a tracking profile that corresponds to a predetermined sinusoidal jitter (SJ) profile and a predetermined phase interpolator (PI) profile. A shift determination can be made for each of a plurality of insertion times according to the tracking profile, the shift determination indicating whether to adjust phase interpolation of the SERDES circuit. At each of the plurality of insertion times, a phase adjustment signal can be generated as a function of the shift determination. For example, the phase adjustment signal can indicate a control code for a phase interpolator coupled to a clock generator of the SERDES, and the signal can be output to the phase interpolator. Some implementations adjust the phase interpolator in response to the phase adjustment signal, such that the phase interpolator injects SJ that substantially tracks the SJ profile.