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1.发明申请CONTINUOUS-TIME SIGMA-DELTA MODULATOR WITH MULTIPLE FEEDBACK PATHS HAVING INDEPENDENT DELAYS 有权具有多个具有独立延迟的反馈条件的连续时间信号调制器公开(公告)号：US20100219999A1
公开(公告)日：2010-09-02
申请号：US12394275
申请日：2009-02-27
申请人： Omid Oliaei , Brandt Braswell
发明人： Omid Oliaei , Brandt Braswell
摘要： Apparatus are provided for continuous-time sigma-delta modulators. A sigma-delta modulator comprises a quantizer configured to convert an analog signal to a digital value. A main feedback arrangement is coupled to the quantizer, and the main feedback arrangement delays the digital value by a first delay period and generates a main feedback signal based on the delayed value. A compensation feedback arrangement is coupled to the quantizer, and compensation feedback arrangement delays the digital value by a second delay period and generates a compensation feedback signal based on the delayed value. A forward signal arrangement produces the analog signal at the quantizer based on an input signal, the main feedback signal, and the compensation feedback signal. The second delay period is independent of and is not influenced by the first delay period, and the second delay period is chosen such that the compensation feedback signal compensates for the first delay period.
摘要翻译： 提供了连续时间Σ-Δ调制器的装置。 Σ-Δ调制器包括被配置为将模拟信号转换为数字值的量化器。 主反馈装置耦合到量化器，并且主反馈装置将数字值延迟第一延迟周期，并且基于延迟值产生主反馈信号。 补偿反馈装置耦合到量化器，并且补偿反馈装置将数字值延迟第二延迟周期，并且基于延迟值产生补偿反馈信号。 正向信号装置基于输入信号，主反馈信号和补偿反馈信号在量化器处产生模拟信号。 第二延迟周期与第一延迟周期无关并且不受第一延迟周期的影响，并且选择第二延迟周期使得补偿反馈信号补偿第一延迟周期。
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2.发明授权Continuous-time sigma-delta modulator with multiple feedback paths having independent delays 有权具有多个具有独立延迟的反馈路径的连续时间Σ-Δ调制器公开(公告)号：US07880654B2
公开(公告)日：2011-02-01
申请号：US12394275
申请日：2009-02-27
申请人： Omid Oliaei , Brandt Braswell
发明人： Omid Oliaei , Brandt Braswell
IPC分类号： H03M3/00
摘要： Apparatus are provided for continuous-time sigma-delta modulators. A sigma-delta modulator comprises a quantizer configured to convert an analog signal to a digital value. A main feedback arrangement is coupled to the quantizer, and the main feedback arrangement delays the digital value by a first delay period and generates a main feedback signal based on the delayed value. A compensation feedback arrangement is coupled to the quantizer, and compensation feedback arrangement delays the digital value by a second delay period and generates a compensation feedback signal based on the delayed value. A forward signal arrangement produces the analog signal at the quantizer based on an input signal, the main feedback signal, and the compensation feedback signal. The second delay period is independent of and is not influenced by the first delay period, and the second delay period is chosen such that the compensation feedback signal compensates for the first delay period.
摘要翻译： 提供了连续时间Σ-Δ调制器的装置。 Σ-Δ调制器包括被配置为将模拟信号转换为数字值的量化器。 主反馈装置耦合到量化器，并且主反馈装置将数字值延迟第一延迟周期，并且基于延迟值产生主反馈信号。 补偿反馈装置耦合到量化器，并且补偿反馈装置将数字值延迟第二延迟周期，并且基于延迟值产生补偿反馈信号。 正向信号装置基于输入信号，主反馈信号和补偿反馈信号在量化器处产生模拟信号。 第二延迟周期与第一延迟周期无关并且不受第一延迟周期的影响，并且选择第二延迟周期使得补偿反馈信号补偿第一延迟周期。
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公开(公告)号：US09264062B1
公开(公告)日：2016-02-16
申请号：US14644941
申请日：2015-03-11
摘要： A digital to analog converter including a current source for providing a master current, a first sub digital to analog converter coupled to the current source which generates a plurality of currents, and a second sub digital to analog converter coupled to at least one of the plurality of currents from the first sub digital to analog converter which generates a second plurality of currents. The digital to analog converter also includes an overlap adjustment circuit coupled with the second sub digital to analog converter which adds current. The digital to analog converter is configured to operate in a first mode for generating a sine wave with a first bit level accuracy and, when in the first mode, the overlap adjustment circuit adds no current. to the second sub digital to analog converter The digital to analog converter is configured to operate in a second mode for generating a ramp wave with a second bit level accuracy and, when in the second mode, the overlap adjustment circuit adds current to the second sub digital to analog converter. When in the second mode, the total current of the second sub digital to analog converter and the overlap converter is greater than one of the plurality of currents generated by the first sub digital to analog converter.
摘要翻译： 一种数模转换器，包括用于提供主电流的电流源，耦合到产生多个电流的电流源的第一子数模转换器，以及耦合到多个电流中的至少一个的第二子数模转换器 从产生第二多个电流的第一子数字到模拟转换器的电流。 数模转换器还包括与第二子数模转换器耦合的重叠调整电路，其增加电流。 数模转换器被配置为以第一模式工作，以产生具有第一位电平精度的正弦波，并且当处于第一模式时，重叠调整电路不加电流。 到第二子数字到模拟转换器数模转换器被配置为在第二模式下操作以产生具有第二位电平精度的斜波，并且当处于第二模式时，重叠调整电路将电流加到第二子电平 数模转换器。 当处于第二模式时，第二子数模转换器和重叠转换器的总电流大于由第一子数模转换器产生的多个电流之一。
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4.发明申请公开(公告)号：US20150244393A1
公开(公告)日：2015-08-27
申请号：US14189841
申请日：2014-02-25
IPC分类号： H03M3/00
摘要： A quantizer for an analog to digital converter has an input for receiving an analog input signal. A detector senses a common mode voltage component of the input signal. A reference voltage source produces a plurality of reference voltages. A voltage source biases the reference voltage source in response to the sensed common mode voltage component. Therefore, the common mode voltage in the input signal establishes the common mode voltage of the reference voltage source. A plurality of comparators are connected to the reference voltage source, wherein each of the plurality of comparators compares the input signal to one of the plurality of reference voltages and produces a output bit denoting a result of the comparing.
摘要翻译： 用于模数转换器的量化器具有用于接收模拟输入信号的输入。 检测器检测输入信号的共模电压分量。 参考电压源产生多个参考电压。 电压源响应于感测的共模电压分量偏置参考电压源。 因此，输入信号中的共模电压建立了参考电压源的共模电压。 多个比较器连接到参考电压源，其中多个比较器中的每一个将输入信号与多个参考电压中的一个进行比较，并产生表示比较结果的输出位。
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5.发明授权Current reduction in a single stage cyclic analog to digital converter with variable resolution 有权具有可变分辨率的单级循环模数转换器的电流降低公开(公告)号：US08264393B2
公开(公告)日：2012-09-11
申请号：US12833597
申请日：2010-07-09
IPC分类号： H03M1/34
摘要： A converter (200) adapted to convert an analog input signal into a digital output signal includes an analog input terminal (205) for receiving the analog input signal, a Redundant Signed Digit (RSD) stage (210) coupled to the analog input terminal, and a digital section (220). The RSD stage is configured to receive the analog input signal at the analog input terminal, produce a first number of bits at a digital output from the analog input signal during a first half of a first clock cycle, provide a residual feedback signal of the analog input signal at the analog input terminal during a second half of the first clock cycle, and produce a second number of bits at the digital output from the residual feedback signal during a first half of a second clock cycle, the second number of bits less than the first number of bits.
摘要翻译： 适于将模拟输入信号转换为数字输出信号的A转换器（200）包括用于接收模拟输入信号的模拟输入端（205），耦合到模拟输入端的冗余有符号（RSD）级（210） 和数字部分（220）。 RSD级被配置为在模拟输入端接收模拟输入信号，在第一时钟周期的前半部分期间，从模拟输入信号的数字输出产生第一位数，提供模拟量的残留反馈信号 在第一时钟周期的后半段期间在模拟输入端子处输入信号，并且在第二时钟周期的前半部分期间从剩余反馈信号在数字输出处产生第二数量的位，第二个位数小于 第一位数。
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公开(公告)号：US20100207797A1
公开(公告)日：2010-08-19
申请号：US12388231
申请日：2009-02-18
申请人： David E. Bien , Brandt Braswell , Merit Y. Hong
发明人： David E. Bien , Brandt Braswell , Merit Y. Hong
CPC分类号： H03M1/0604 , H03M1/365 , H03M7/165
摘要： Apparatus and methods are provided for converting an analog input signal to a digital output value. A quantization circuit comprises an input node and a comparator array, wherein each comparator of the comparator array is coupled to the input node. A voltage divider arrangement is coupled to the comparator array and configured to establish a respective threshold voltage for each comparator of the comparator array. The comparator array generates a digital code based on the input signal and the respective threshold voltage for each comparator. A control node is coupled to the voltage divider arrangement, wherein the control node and the voltage divider arrangement are cooperatively configured to adjust the threshold voltage for at least one comparator of the comparator array in response to a control signal at the control node.
摘要翻译： 提供了用于将模拟输入信号转换为数字输出值的装置和方法。 量化电路包括输入节点和比较器阵列，其中比较器阵列的每个比较器耦合到输入节点。 分压器布置耦合到比较器阵列并且被配置为为比较器阵列的每个比较器建立相应的阈值电压。 比较器阵列基于每个比较器的输入信号和相应的阈值电压产生数字码。 控制节点耦合到分压器装置，其中协调地配置控制节点和分压器装置以响应于控制节点处的控制信号来调整比较器阵列的至少一个比较器的阈值电压。
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公开(公告)号：US20090033371A1
公开(公告)日：2009-02-05
申请号：US12244214
申请日：2008-10-02
申请人： Brandt Braswell , David R. LoCascio
发明人： Brandt Braswell , David R. LoCascio
IPC分类号： H03K5/22
CPC分类号： G11C27/026
摘要： A double sampled switched capacitor architecture as described herein includes an amplifier having two separate inputs corresponding to two separate amplifier sections. The amplifier uses a first differential transistor pair for the first amplifier section, a second differential transistor pair for the second amplifier section, a first tail current bias arrangement for the first differential transistor pair, and a second tail current bias arrangement for the second differential transistor pair. The tail current bias arrangements are driven by a bias switching architecture that alternately activates one tail current bias arrangement while at least partially deactivating the other tail current bias arrangement. The amplifier and bias switching architecture cooperate to eliminate gain error that would otherwise be caused by a common parasitic capacitance shared by a single amplifier section.
摘要翻译： 如本文所述的双采样开关电容器架构包括具有对应于两个单独的放大器部分的两个单独输入的放大器。 放大器使用用于第一放大器部分的第一差分晶体管对，用于第二放大器部分的第二差分晶体管对，用于第一差分晶体管对的第一尾电流偏置装置，以及用于第二差分晶体管的第二尾电流偏置装置 对。 尾电流偏置装置由偏置开关结构驱动，交替地激活一个尾电流偏压装置，同时至少部分地去激活另一尾电流偏置装置。 放大器和偏置开关结构协调以消除否则将由单个放大器部分共享的公共寄生电容引起的增益误差。
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公开(公告)号：US07282929B2
公开(公告)日：2007-10-16
申请号：US11493686
申请日：2006-07-25
IPC分类号： G01R27/08
CPC分类号： G01R19/0023 , G01R1/203
摘要： Apparatus for sensing a current across a known resistor comprising a switched capacitor network and an amplifier having an input coupled to an output of the switched capacitor network. The switched capacitor network is configured to sample first and second reference potentials indicating the current. The amplifier is configured to produce first and second amplified potentials at an output of the amplifier based on the first and second reference potentials.
摘要翻译： 用于感测跨过已知电阻器的电流的装置，包括开关电容器网络和具有耦合到开关电容器网络的输出的输入端的放大器。 开关电容器网络被配置为对指示电流的第一和第二参考电位进行采样。 放大器被配置为基于第一和第二参考电位在放大器的输出处产生第一和第二放大电位。
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公开(公告)号：US07190279B2
公开(公告)日：2007-03-13
申请号：US11063957
申请日：2005-02-22
CPC分类号： G08B1/08
摘要： A light modulation system as described herein can be incorporated into a personal or portable electronic apparatus such as a cellular telephone, a digital music player, or the like. The light modulation system controls the activation of light elements, such as light emitting diodes, of the host electronic apparatus in response to one or more analog audio signals available at the host electronic apparatus. The analog audio signals may be obtained from any suitable analog audio path or source in the host electronic apparatus. The light modulation system is compact, inexpensive to implement, and need not rely on digital signal processors for operation.
摘要翻译： 如本文所述的光调制系统可以并入到诸如蜂窝电话，数字音乐播放器等的个人或便携式电子设备中。 光调制系统响应于在主机电子设备处可用的一个或多个模拟音频信号来控制主机电子设备的光元件（例如发光二极管）的激活。 模拟音频信号可以从主机电子设备中的任何合适的模拟音频路径或源获得。 光调制系统紧凑，实施成本低廉，不需要依靠数字信号处理器进行操作。
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10.发明授权公开(公告)号：US09148169B2
公开(公告)日：2015-09-29
申请号：US14189841
申请日：2014-02-25
IPC分类号： H03M3/00
摘要： A quantizer for an analog to digital converter has an input for receiving an analog input signal. A detector senses a common mode voltage component of the input signal. A reference voltage source produces a plurality of reference voltages. A voltage source biases the reference voltage source in response to the sensed common mode voltage component. Therefore, the common mode voltage in the input signal establishes the common mode voltage of the reference voltage source. A plurality of comparators are connected to the reference voltage source, wherein each of the plurality of comparators compares the input signal to one of the plurality of reference voltages and produces a output bit denoting a result of the comparing.
摘要翻译： 用于模数转换器的量化器具有用于接收模拟输入信号的输入。 检测器检测输入信号的共模电压分量。 参考电压源产生多个参考电压。 电压源响应于感测的共模电压分量偏置参考电压源。 因此，输入信号中的共模电压建立了参考电压源的共模电压。 多个比较器连接到参考电压源，其中多个比较器中的每个比较器将输入信号与多个参考电压中的一个进行比较，并产生表示比较结果的输出位。
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