Receiver with feedback continuous-time delta-sigma modulator with current-mode input
    1.
    发明授权
    Receiver with feedback continuous-time delta-sigma modulator with current-mode input 失效
    具有反馈连续时间Δ-Σ调制器的接收器,具有电流模式输入

    公开(公告)号:US08711980B2

    公开(公告)日:2014-04-29

    申请号:US12879477

    申请日:2010-09-10

    申请人: Omid Oliaei

    发明人: Omid Oliaei

    IPC分类号: H03K9/00

    摘要: In accordance with some embodiments of the present disclosure, a receiver may include a downconverter configured to demodulate a modulated wireless signal to produce a current-mode baseband signal and an analog-to-digital converter (ADC) configured to convert the current-mode baseband signal into a digital output signal. The downconverter may be coupled to the ADC without an intervening filter element.

    摘要翻译: 根据本公开的一些实施例,接收机可以包括下变频器,其被配置为解调调制的无线信号以产生电流模式基带信号;以及模数转换器(ADC),其被配置为将当前模式基带 信号转换为数字输出信号。 下变频器可以耦合到ADC而没有中间滤波器元件。

    System and method for preserving input impedance of a current-mode circuit
    2.
    发明授权
    System and method for preserving input impedance of a current-mode circuit 有权
    用于保持电流模式电路的输入阻抗的系统和方法

    公开(公告)号:US08463206B2

    公开(公告)日:2013-06-11

    申请号:US13207672

    申请日:2011-08-11

    IPC分类号: H04B1/04

    CPC分类号: H03F3/193

    摘要: In accordance with some embodiments of the present disclosure, a circuit comprises an input node configured to receive a current-mode input signal and an input stage that includes an input device communicatively coupled to the input node. The input device is configured to receive the input signal at the input node. The circuit additionally comprises bias circuitry communicatively coupled to the input stage and configured to provide a bias current for the input device. The bias circuitry is also configured to remove at least a portion of the bias current from the input signal through a feedback loop associated with the input node such that the input signal is received by the input device with at least a portion of the bias current removed. The circuit further comprises an output stage communicatively coupled to the input stage and configured to output a current-mode output signal based on the input signal.

    摘要翻译: 根据本公开的一些实施例,电路包括被配置为接收电流模式输入信号的输入节点和包括通信地耦合到输入节点的输入设备的输入级。 输入设备被配置为在输入节点处接收输入信号。 电路还包括通信地耦合到输入级并被配置为为输入设备提供偏置电流的偏置电路。 偏置电路还被配置为通过与输入节点相关联的反馈回路从输入信号中去除偏置电流的至少一部分,使得输入信号由输入装置接收,其中偏置电流的至少一部分被去除 。 电路还包括通信地耦合到输入级并被配置为基于输入信号输出电流模式输出信号的输出级。

    Digital voltage-controlled attenuator
    3.
    发明授权
    Digital voltage-controlled attenuator 有权
    数字电压控制衰减器

    公开(公告)号:US08447256B2

    公开(公告)日:2013-05-21

    申请号:US13207649

    申请日:2011-08-11

    IPC分类号: H04B1/18 H03H5/00 H01P1/00

    CPC分类号: H03H7/25

    摘要: In accordance with some embodiments of the present disclosure an attenuating circuit comprises a balun configured to receive a radio frequency (RF) signal at first and second input ports and configured to output the RF signal. The circuit further comprises an attenuator coupled in parallel with the first and second input ports. A power level of the RF signal output by the balun is based at least partially on an impedance of the attenuator. The attenuator comprises a resistor ladder configured to receive at least a portion of the RF signal and a plurality of switches coupled to the resistor ladder. The plurality of switches are configured to open and close such that the impedance of the attenuator is a function of which switches are open and closed. Therefore, the power of the RF signal is controlled based at least on the opening and closing of the switches.

    摘要翻译: 根据本公开的一些实施例,衰减电路包括被配置为在第一和第二输入端口处接收射频(RF)信号并被配置为输出RF信号的平衡 - 不平衡变换器。 电路还包括与第一和第二输入端口并联耦合的衰减器。 由平衡 - 不平衡变换器输出的RF信号的功率电平至少部分地基于衰减器的阻抗。 衰减器包括被配置为接收RF信号的至少一部分的电阻器梯形以及耦合到电阻器梯的多个开关。 多个开关被配置为打开和关闭,使得衰减器的阻抗是开关闭合的功能。 因此,至少基于开关的打开和关闭来控制RF信号的功率。

    System and Method for Multiple Band Transmission
    4.
    发明申请
    System and Method for Multiple Band Transmission 有权
    多频带传输的系统和方法

    公开(公告)号:US20120081203A1

    公开(公告)日:2012-04-05

    申请号:US12895086

    申请日:2010-09-30

    IPC分类号: H01F27/29

    CPC分类号: H01F27/29 H01F19/04

    摘要: In accordance with embodiments of the present disclosure, a multi-tap integrated transformer may include one or more windings, wherein each of the one or more windings include at least one pair of primary taps for receiving at least one differential input signal, a first pair of secondary taps for outputting a first output signal, and a second pair of secondary taps for outputting a second output signal. The first and second output signals may be based on the at least one differential input signal and a mutual inductance between portions of the one or more windings associated with the at least one pair of primary taps, the first pair of secondary taps, and the second pair of secondary taps.

    摘要翻译: 根据本公开的实施例,多抽头集成变压器可以包括一个或多个绕组,其中一个或多个绕组中的每个绕组包括用于接收至少一个差分输入信号的至少一对主抽头,第一对 用于输出第一输出信号的第二抽头和用于输出第二输出信号的第二对次级抽头。 所述第一和第二输出信号可以基于所述至少一个差分输入信号和与所述至少一对主抽头,所述第一对次级​​抽头相关联的所述一个或多个绕组的所述部分之间的互感, 一对二次水龙头。

    Continuous-time image-reject filter with discrete-time feedback
    5.
    发明授权
    Continuous-time image-reject filter with discrete-time feedback 有权
    具有离散时间反馈的连续图像抑制滤波器

    公开(公告)号:US07999709B2

    公开(公告)日:2011-08-16

    申请号:US12534650

    申请日:2009-08-03

    申请人: Omid Oliaei

    发明人: Omid Oliaei

    IPC分类号: H03M3/00

    摘要: Apparatus are provided for converting a discrete-time analog signal to a continuous-time analog signal. A module comprises a digital-to-analog converter and a filtering arrangement coupled between the digital-to-analog converter and an output node. The digital-to-analog converter converts a digital signal to a discrete-time analog signal. The filtering arrangement comprises a forward signal arrangement having an input configured to receive the discrete-time analog signal and a feedback signal arrangement coupled to the forward signal arrangement. The feedback signal arrangement generates a discrete-time feedback signal at the input of the forward signal arrangement based on one or more continuous-time analog signals from the forward signal arrangement. The forward signal arrangement generates the continuous-time analog output signal at the output node based on a difference between the discrete-time analog signal and the discrete-time feedback signal.

    摘要翻译: 提供了用于将离散时间模拟信号转换为连续时间模拟信号的装置。 模块包括耦合在数模转换器和输出节点之间的数模转换器和滤波装置。 数模转换器将数字信号转换为离散时间模拟信号。 滤波装置包括具有被配置为接收离散时间模拟信号的输入端和耦合到正向信号装置的反馈信号装置的正向信号装置。 反馈信号装置基于来自正向信号装置的一个或多个连续时间模拟信号在正向信号装置的输入处产生离散时间反馈信号。 正向信号装置基于离散时间模拟信号和离散时间反馈信号之间的差异在输出节点处产生连续时间模拟输出信号。

    CONTINUOUS-TIME SIGMA-DELTA MODULATOR WITH MULTIPLE FEEDBACK PATHS HAVING INDEPENDENT DELAYS
    6.
    发明申请
    CONTINUOUS-TIME SIGMA-DELTA MODULATOR WITH MULTIPLE FEEDBACK PATHS HAVING INDEPENDENT DELAYS 有权
    具有多个具有独立延迟的反馈条件的连续时间信号调制器

    公开(公告)号:US20100219999A1

    公开(公告)日:2010-09-02

    申请号:US12394275

    申请日:2009-02-27

    IPC分类号: H03M3/02 H03M1/66

    CPC分类号: H03M3/374 H03M3/454

    摘要: Apparatus are provided for continuous-time sigma-delta modulators. A sigma-delta modulator comprises a quantizer configured to convert an analog signal to a digital value. A main feedback arrangement is coupled to the quantizer, and the main feedback arrangement delays the digital value by a first delay period and generates a main feedback signal based on the delayed value. A compensation feedback arrangement is coupled to the quantizer, and compensation feedback arrangement delays the digital value by a second delay period and generates a compensation feedback signal based on the delayed value. A forward signal arrangement produces the analog signal at the quantizer based on an input signal, the main feedback signal, and the compensation feedback signal. The second delay period is independent of and is not influenced by the first delay period, and the second delay period is chosen such that the compensation feedback signal compensates for the first delay period.

    摘要翻译: 提供了连续时间Σ-Δ调制器的装置。 Σ-Δ调制器包括被配置为将模拟信号转换为数字值的量化器。 主反馈装置耦合到量化器,并且主反馈装置将数字值延迟第一延迟周期,并且基于延迟值产生主反馈信号。 补偿反馈装置耦合到量化器,并且补偿反馈装置将数字值延迟第二延迟周期,并且基于延迟值产生补偿反馈信号。 正向信号装置基于输入信号,主反馈信号和补偿反馈信号在量化器处产生模拟信号。 第二延迟周期与第一延迟周期无关并且不受第一延迟周期的影响,并且选择第二延迟周期使得补偿反馈信号补偿第一延迟周期。

    DIGITAL VOLTAGE-CONTROLLED ATTENUATOR
    8.
    发明申请
    DIGITAL VOLTAGE-CONTROLLED ATTENUATOR 有权
    数字电压控制衰减器

    公开(公告)号:US20130040591A1

    公开(公告)日:2013-02-14

    申请号:US13207649

    申请日:2011-08-11

    IPC分类号: H04W88/02

    CPC分类号: H03H7/25

    摘要: In accordance with some embodiments of the present disclosure an attenuating circuit comprises a balun configured to receive a radio frequency (RF) signal at first and second input ports and configured to output the RF signal. The circuit further comprises an attenuator coupled in parallel with the first and second input ports. A power level of the RF signal output by the balun is based at least partially on an impedance of the attenuator. The attenuator comprises a resistor ladder configured to receive at least a portion of the RF signal and a plurality of switches coupled to the resistor ladder. The plurality of switches are configured to open and close such that the impedance of the attenuator is a function of which switches are open and closed. Therefore, the power of the RF signal is controlled based at least on the opening and closing of the switches.

    摘要翻译: 根据本公开的一些实施例,衰减电路包括被配置为在第一和第二输入端口处接收射频(RF)信号并被配置为输出RF信号的平衡 - 不平衡变换器。 电路还包括与第一和第二输入端口并联耦合的衰减器。 由平衡 - 不平衡变换器输出的RF信号的功率电平至少部分地基于衰减器的阻抗。 衰减器包括被配置为接收RF信号的至少一部分的电阻器梯形以及耦合到电阻器梯的多个开关。 多个开关被配置为打开和关闭,使得衰减器的阻抗是开关闭合的功能。 因此,至少基于开关的打开和关闭来控制RF信号的功率。

    System and Method for Switch Leakage Cancellation
    10.
    发明申请
    System and Method for Switch Leakage Cancellation 有权
    开关泄漏消除系统和方法

    公开(公告)号:US20120062307A1

    公开(公告)日:2012-03-15

    申请号:US12882306

    申请日:2010-09-15

    IPC分类号: H03K17/687

    CPC分类号: H03K17/165 H03K2217/0036

    摘要: In accordance with embodiments of the present disclosure, a circuit may include a transmission switch and a dummy switch coupled at its output to the output of the transmission switch. The transmission switch may be configured to be selectively enabled and disabled based on a control signal received at a gate of the transmission switch. The transmission switch may be further configured to receive a first polarity of a differential signal at its input and pass the first polarity of the differential signal to its output when enabled. The dummy switch may be configured to be disabled and to receive a second polarity of the differential signal at its input, the second polarity of opposite polarity of the first polarity.

    摘要翻译: 根据本公开的实施例,电路可以包括传输开关和在其输出处耦合到传输开关的输出的虚拟开关。 传输开关可以被配置为基于在传输交换机的门处接收的控制信号来选择性地使能和禁用。 传输开关还可以被配置为在其输入处接收差分信号的第一极性,并且当使能时将差分信号的第一极性传递到其输出。 伪开关可以被配置为禁用,并且在其输入处接收差分信号的第二极性,第二极性与第一极性相反的极性。