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1.发明授权Analog to digital conversion architecture and method with input and reference voltage scaling 有权具有输入和参考电压缩放的模数转换结构和方法公开(公告)号：US08823566B2
公开(公告)日：2014-09-02
申请号：US13537308
申请日：2012-06-29
IPC分类号： H03M1/88
摘要： An analog-to-digital converter stage includes: a comparator and logic circuit having first upper and lower unscaled voltage trip points that are different than upper and lower residue voltage trip points; and a switched capacitor circuit. The comparator and logic circuit is configured prior to an initial residue calculation cycle to compare a magnitude of an unscaled input voltage to the first upper and lower unscaled voltage trip points, to generate an initial output bit, and to generate a voltage scaling and gain control signal. The switched capacitor circuit is configured to sample the unscaled input voltage, to receive a reference voltage, and to receive the voltage scaling and gain control signal for selectively controlling a subset of switches of the switched capacitor circuit to scale the unscaled input voltage sample and reference voltage and generate an initial residue voltage during a single operation of the initial residue calculation cycle.
摘要翻译： 模数转换器级包括：比较器和逻辑电路，具有不同于上残留电压跳变点和下残余电压跳变点的第一上和下非放大电压跳变点; 和开关电容电路。 比较器和逻辑电路在初始残余计算周期之前配置，以将未缩放输入电压的幅度与第一上限和下限未缩放电压跳变点进行比较，以产生初始输出位，并产生电压缩放和增益控制 信号。 开关电容器电路被配置为对未缩放的输入电压进行采样以接收参考电压，并且接收电压调节和增益控制信号，以选择性地控制开关电容器电路的开关的子集，以缩放未缩放的输入电压样本和参考 并且在初始残留计算周期的单次操作期间产生初始残留电压。
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公开(公告)号：US08710896B2
公开(公告)日：2014-04-29
申请号：US13484304
申请日：2012-05-31
IPC分类号： H03L5/00 , H03K19/0185
CPC分类号： H03K19/018521
摘要： A sampling switch circuit uses correlated level shifting. The sampling switch circuit includes: a sampling switch having a first terminal, a control terminal, and an output terminal, wherein the first terminal is connected to an input voltage node; a boosting circuit connected to first and second supply voltage nodes and coupled to the control terminal of the sampling switch; and a correlated level shifting buffer circuit. The correlated level shifting buffer circuit includes: an amplifier having first and second inputs and an output, wherein the first input is connected to the input voltage node, and the output and second input are coupled to the boosting circuit; and a level shifting capacitor coupled to the second input and output of the amplifier, to the boosting circuit, and to a level shifting voltage node.
摘要翻译： 采样开关电路使用相关电平转换。 采样开关电路包括：具有第一端子，控制端子和输出端子的采样开关，其中第一端子连接到输入电压节点; 连接到第一和第二电源电压节点并耦合到采样开关的控制端的升压电路; 和相关电平移位缓冲电路。 相关电平移位缓冲电路包括：具有第一和第二输入和输出的放大器，其中第一输入连接到输入电压节点，输出和第二输入耦合到升压电路; 以及耦合到放大器的第二输入和输出，升压电路以及电平转换电压节点的电平移动电容器。
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公开(公告)号：US20130321059A1
公开(公告)日：2013-12-05
申请号：US13484304
申请日：2012-05-31
IPC分类号： H03L5/00
CPC分类号： H03K19/018521
摘要： A sampling switch circuit uses correlated level shifting. The sampling switch circuit includes: a sampling switch having a first terminal, a control terminal, and an output terminal, wherein the first terminal is connected to an input voltage node; a boosting circuit connected to first and second supply voltage nodes and coupled to the control terminal of the sampling switch; and a correlated level shifting buffer circuit. The correlated level shifting buffer circuit includes: an amplifier having first and second inputs and an output, wherein the first input is connected to the input voltage node, and the output and second input are coupled to the boosting circuit; and a level shifting capacitor coupled to the second input and output of the amplifier, to the boosting circuit, and to a level shifting voltage node.
摘要翻译： 采样开关电路使用相关电平转换。 采样开关电路包括：具有第一端子，控制端子和输出端子的采样开关，其中第一端子连接到输入电压节点; 连接到第一和第二电源电压节点并耦合到采样开关的控制端的升压电路; 和相关电平移位缓冲电路。 相关电平移位缓冲电路包括：具有第一和第二输入和输出的放大器，其中第一输入连接到输入电压节点，输出和第二输入耦合到升压电路; 以及耦合到放大器的第二输入和输出，升压电路以及电平转换电压节点的电平移动电容器。
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4.发明申请CURRENT REDUCTION IN A SINGLE STAGE CYCLIC ANALOG TO DIGITAL CONVERTER WITH VARIABLE RESOLUTION 有权在单阶段循环模式下的电流减少到具有可变分辨率的数字转换器公开(公告)号：US20120007762A1
公开(公告)日：2012-01-12
申请号：US12833597
申请日：2010-07-09
IPC分类号： H03M1/34
摘要： A converter (200) adapted to convert an analog input signal into a digital output signal includes an analog input terminal (205) for receiving the analog input signal, a Redundant Signed Digit (RSD) stage (210) coupled to the analog input terminal, and a digital section (220). The RSD stage is configured to receive the analog input signal at the analog input terminal, produce a first number of bits at a digital output from the analog input signal during a first half of a first clock cycle, provide a residual feedback signal of the analog input signal at the analog input terminal during a second half of the first clock cycle, and produce a second number of bits at the digital output from the residual feedback signal during a first half of a second clock cycle, the second number of bits less than the first number of bits.
摘要翻译： 适于将模拟输入信号转换为数字输出信号的A转换器（200）包括用于接收模拟输入信号的模拟输入端（205），耦合到模拟输入端的冗余有符号（RSD）级（210） 和数字部分（220）。 RSD级被配置为在模拟输入端接收模拟输入信号，在第一时钟周期的前半部分期间，从模拟输入信号的数字输出产生第一位数，提供模拟量的残留反馈信号 在第一时钟周期的后半段期间在模拟输入端子处输入信号，并且在第二时钟周期的前半部分期间，从剩余反馈信号在数字输出处产生第二数量的位，第二个位数小于 第一位数。
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5.发明申请ANALOG TO DIGITAL CONVERSION ARCHITECTURE AND METHOD WITH INPUT AND REFERENCE VOLTAGE SCALING 有权模拟数字转换架构和输入和参考电压范围的方法公开(公告)号：US20140002291A1
公开(公告)日：2014-01-02
申请号：US13537308
申请日：2012-06-29
IPC分类号： H03M1/12
摘要： An analog-to-digital converter stage includes: a comparator and logic circuit having first upper and lower unscaled voltage trip points that are different than upper and lower residue voltage trip points; and a switched capacitor circuit. The comparator and logic circuit is configured prior to an initial residue calculation cycle to compare a magnitude of an unscaled input voltage to the first upper and lower unscaled voltage trip points, to generate an initial output bit, and to generate a voltage scaling and gain control signal. The switched capacitor circuit is configured to sample the unscaled input voltage, to receive a reference voltage, and to receive the voltage scaling and gain control signal for selectively controlling a subset of switches of the switched capacitor circuit to scale the unscaled input voltage sample and reference voltage and generate an initial residue voltage during a single operation of the initial residue calculation cycle.
摘要翻译： 模数转换器级包括：比较器和逻辑电路，具有不同于上残留电压跳变点和下残余电压跳变点的第一上和下非放大电压跳变点; 和开关电容电路。 比较器和逻辑电路在初始残余计算周期之前配置，以将未缩放输入电压的幅度与第一上限和下限未缩放电压跳变点进行比较，以产生初始输出位，并产生电压缩放和增益控制 信号。 开关电容器电路被配置为对未缩放的输入电压进行采样以接收参考电压，并且接收电压调节和增益控制信号，以选择性地控制开关电容器电路的开关的子集，以缩放未缩放的输入电压样本和参考 并且在初始残留计算周期的单次操作期间产生初始残留电压。
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公开(公告)号：US08471749B2
公开(公告)日：2013-06-25
申请号：US13185059
申请日：2011-07-18
IPC分类号： H03M1/12
CPC分类号： H03K5/2481 , H03K5/249
摘要： A comparator is provided. In one embodiment, a method of operating a comparator comprises providing a bias current (920); comparing an input signal and a reference signal to determine a difference signal and an inverted difference signal (930); latching the difference signal and the inverted difference signal to generate a first and second latched signals (950); generating a control signal using at least the first and second latched signals (970); and controlling the bias current in response to the control signal (980), wherein the comparing the input signal and the reference signal (930) is activated and deactivated in response to the controlling the bias current (980). In another embodiment, a comparator comprises a bias circuit (420) configured to provide a bias current; a comparator circuit (430) configured to determine a difference signal and an inverted difference signal by comparing an input signal and a reference signal, wherein the bias current is used to place the comparator circuit (430) in an active mode; a latch circuit (450) configured to latch the difference signal and the inverted difference signal to generate a first and second latched signals; a control circuit (470) configured to generate a control signal using at least the first and second latched signals; and a switch circuit (480) configured to use the control signal to control the bias current to place the comparator circuit (430) in an active mode and an inactive mode.
摘要翻译： 提供一个比较器。 在一个实施例中，操作比较器的方法包括提供偏置电流（920）; 比较输入信号和参考信号以确定差信号和反相差信号（930）; 锁存差分信号和反相差信号以产生第一和第二锁存信号（950）; 使用至少所述第一和第二锁存信号产生控制信号（970）; 以及响应于所述控制信号（980）控制所述偏置电流，其中响应于所述偏置电流的控制来激活和去激活所述输入信号和所述参考信号（930）。 在另一个实施例中，比较器包括被配置为提供偏置电流的偏置电路（420） 比较器电路（430），被配置为通过比较输入信号和参考信号来确定差分信号和反相差信号，其中偏置电流用于将比较器电路（430）置于有效模式; 锁存电路（450），被配置为锁存所述差分信号和所述反相差信号以产生第一和第二锁存信号; 配置为使用至少所述第一和第二锁存信号来产生控制信号的控制电路（470） 以及配置为使用所述控制信号来控制所述偏置电流以将所述比较器电路（430）置于活动模式和非活动模式的开关电路（480）。
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7.发明申请ANALOG-TO-DIGITAL CONVERTER HAVING A SINGLE SET OF COMPARATORS FOR A MULTI-STAGE SAMPLING CIRCUIT AND METHOD THEREFOR 有权具有多级采样电路的单组比较器的模数转数转换器及其方法公开(公告)号：US20120026026A1
公开(公告)日：2012-02-02
申请号：US12846589
申请日：2010-07-29
IPC分类号： H03M1/34
CPC分类号： H03M1/1225 , H03M1/0675 , H03M1/403 , H03M1/442
摘要： An analog to digital converter includes a first sample circuit that samples an analog input during a first phase of a clock. A second sample circuit samples the analog input during a second phase of the clock. A comparator compares a reference to the output of the first sample circuit during a non-overlapping time between an end of the first phase and beginning of the second phase and compares the reference to the output of the second sample circuit during a non-overlapping time between an end of the second phase and beginning of the first phase. The first sample circuit couples the sample of the analog input taken by the first sample circuit to the input of the comparator during the non-overlapping time between the end of the first phase and the beginning of the second phase and the second sample circuit couples the sample of the analog input taken by the second sample circuit to the input of the comparator during the non-overlapping time between the end of the second phase and the beginning of the first phase.
摘要翻译： 模数转换器包括在时钟的第一阶段期间对模拟输入进行采样的第一采样电路。 第二采样电路在时钟的第二阶段对模拟输入进行采样。 比较器在第一阶段的结束与第二阶段的开始之间的非重叠时间期间比较第一采样电路的输出的参考，并且在不重叠时间期间比较参考与第二采样电路的输出 在第二阶段的结束和第一阶段的开始之间。 第一采样电路将第一采样电路所采用的模拟输入的采样与比较器的输入端在第一阶段的结束和第二阶段的开始之间的非重叠时间期间耦合，并且第二采样电路将 在第二阶段结束和第一阶段开始之间的非重叠时间期间，由第二采样电路获取的模拟输入的采样到比较器的输入。
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公开(公告)号：US20130285705A1
公开(公告)日：2013-10-31
申请号：US13455400
申请日：2012-04-25
IPC分类号： G11C27/02
CPC分类号： G11C27/02 , G11C27/024 , G11C27/026
摘要： A sample and hold circuit is provided. The circuit includes a plurality of switches, a first capacitor, an operational amplifier having a first input selectively coupled to the first capacitor and an output, a second capacitor and a third capacitor both selectively coupled to the first capacitor and both selectively coupled between the first input of the operational amplifier and the output of the operational amplifier, wherein the plurality of switches are configured to receive a plurality of control signals such that the first capacitor is configured to sample an input signal in a sample phase and to transfer a charge to one of the second capacitor and the third capacitor in a hold phase, and the second capacitor and third capacitor are configured to alternate between holding the transferred charge and resetting in any back-to-back hold phases.
摘要翻译： 提供采样和保持电路。 该电路包括多个开关，第一电容器，运算放大器，其具有选择性地耦合到第一电容器的第一输入端和输出端，第二电容器和第三电容器，两者选择性地耦合到第一电容器，并且两者选择性地耦合在第一电容器 运算放大器的输入和运算放大器的输出，其中多个开关被配置为接收多个控制信号，使得第一电容器被配置为对采样相位中的输入信号进行采样并将电荷转移到一个 所述第二电容器和所述第三电容器处于保持阶段，并且所述第二电容器和第三电容器被配置为在保持所传送的电荷和在任何背对背保持阶段中的复位之间交替。
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公开(公告)号：US20130021189A1
公开(公告)日：2013-01-24
申请号：US13185059
申请日：2011-07-18
CPC分类号： H03K5/2481 , H03K5/249
摘要： A comparator is provided. In one embodiment, a method of operating a comparator comprises providing a bias current (920); comparing an input signal and a reference signal to determine a difference signal and an inverted difference signal (930); latching the difference signal and the inverted difference signal to generate a first and second latched signals (950); generating a control signal using at least the first and second latched signals (970); and controlling the bias current in response to the control signal (980), wherein the comparing the input signal and the reference signal (930) is activated and deactivated in response to the controlling the bias current (980). In another embodiment, a comparator comprises a bias circuit (420) configured to provide a bias current; a comparator circuit (430) configured to determine a difference signal and an inverted difference signal by comparing an input signal and a reference signal, wherein the bias current is used to place the comparator circuit (430) in an active mode; a latch circuit (450) configured to latch the difference signal and the inverted difference signal to generate a first and second latched signals; a control circuit (470) configured to generate a control signal using at least the first and second latched signals; and a switch circuit (480) configured to use the control signal to control the bias current to place the comparator circuit (430) in an active mode and an inactive mode,
摘要翻译： 提供一个比较器。 在一个实施例中，操作比较器的方法包括提供偏置电流（920）; 比较输入信号和参考信号以确定差信号和反相差信号（930）; 锁存差分信号和反相差信号以产生第一和第二锁存信号（950）; 使用至少所述第一和第二锁存信号产生控制信号（970）; 以及响应于所述控制信号（980）控制所述偏置电流，其中响应于所述偏置电流的控制来激活和去激活所述输入信号和所述参考信号（930）。 在另一个实施例中，比较器包括被配置为提供偏置电流的偏置电路（420） 比较器电路（430），被配置为通过比较输入信号和参考信号来确定差分信号和反相差信号，其中偏置电流用于将比较器电路（430）置于有效模式; 锁存电路（450），被配置为锁存所述差分信号和所述反相差信号以产生第一和第二锁存信号; 配置为使用至少所述第一和第二锁存信号来产生控制信号的控制电路（470） 以及开关电路（480），被配置为使用所述控制信号来控制所述偏置电流以将所述比较器电路（430）置于活动模式和非活动模式，
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10.发明申请SWITCHED-CAPACITOR CIRCUITS, INTEGRATION SYSTEMS, AND METHODS OF OPERATION THEREOF 有权开关电容电路，集成系统及其运行方法公开(公告)号：US20100194612A1
公开(公告)日：2010-08-05
申请号：US12363201
申请日：2009-01-30
摘要： Embodiments include integrator systems, switched-capacitor circuits, and methods of their operation. An integrator system comprises a differential amplifier and first and second sampling modules. The first sampling module includes a first capacitor and a first set of switches. The first set of switches changes a connection status between the first capacitor and first and second amplifier input terminals when a change in a polarity of a differential input signal does not occur between consecutive switching cycles, and refrains from changing the connection status when the change in the polarity does occur. The second sampling module includes a second capacitor and a second set of switches. The second set of switches changes a connection status between the second capacitor and the first and second amplifier input terminals when the change in the polarity does occur, and refrains from changing the connection status when the change in the polarity does not occur.
摘要翻译： 实施例包括积分器系统，开关电容器电路及其操作方法。 积分器系统包括差分放大器和第一和第二采样模块。 第一采样模块包括第一电容器和第一组开关。 当在连续的开关周期之间不发生差分输入信号的极性的变化时，第一组开关改变第一电容器与第一和第二放大器输入端子之间的连接状态，并且当改变连接状态时不改变连接状态 极性确实发生。 第二采样模块包括第二电容器和第二组开关。 当发生极性变化时，第二组开关改变第二电容器与第一和第二放大器输入端子之间的连接状态，并且当不发生极性变化时，不改变连接状态。
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