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公开(公告)号：US5606313A
公开(公告)日：1997-02-25
申请号：US558619
申请日：1995-11-14
CPC分类号： H04M19/08 , H04W52/0229 , Y02B60/50
摘要： An electronic tag (10) receives a data message (18) that has a wake-up section (20) followed by a session section (22). The interrogation signal which carries the data message encodes the wake-up section (20) differently from the session section (22). A power manager (28) decodes the wake-up section (20) using a very low power decoder (34) that remains energized during a standby state. When the power manager (28) detects a predetermined identification code (26), it controls a switching circuit (32) to energize a controller (30). The controller (30) may then decode, process, and respond to information conveyed during the session section (22). If the power manager (28) does not detect the identification code (26), the controller (30) remains de-energized. The power manager (28) also includes a synchronizer (38) which determines when a preamble (24) is detected, and an ID decoder (40) that determines when the wake-up section (20) conveys the predetermined identification code (26).
摘要翻译： 电子标签（10）接收具有唤醒部分（20）的跟随着会话部分（22）的数据消息（18）。 携带数据消息的询问信号与会话部分（22）不同地编码唤醒部分（20）。 功率管理器（28）使用在待机状态期间保持通电的极低功率解码器（34）来解码唤醒部分（20）。 当功率管理器（28）检测到预定的识别码（26）时，控制切换电路（32）使控制器（30）通电。 然后，控制器（30）可以解码，处理和响应在会话段（22）期间传送的信息。 如果电源管理器（28）没有检测到识别码（26），则控制器（30）保持断电。 功率管理器（28）还包括一个确定何时检测到前置码（24）的同步器（38），以及一个确定唤醒部分（20）何时传送预定识别码（26）的ID解码器（40） 。
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2.发明申请ANALOG TO DIGITAL CONVERSION ARCHITECTURE AND METHOD WITH INPUT AND REFERENCE VOLTAGE SCALING 有权模拟数字转换架构和输入和参考电压范围的方法公开(公告)号：US20140002291A1
公开(公告)日：2014-01-02
申请号：US13537308
申请日：2012-06-29
IPC分类号： H03M1/12
摘要： An analog-to-digital converter stage includes: a comparator and logic circuit having first upper and lower unscaled voltage trip points that are different than upper and lower residue voltage trip points; and a switched capacitor circuit. The comparator and logic circuit is configured prior to an initial residue calculation cycle to compare a magnitude of an unscaled input voltage to the first upper and lower unscaled voltage trip points, to generate an initial output bit, and to generate a voltage scaling and gain control signal. The switched capacitor circuit is configured to sample the unscaled input voltage, to receive a reference voltage, and to receive the voltage scaling and gain control signal for selectively controlling a subset of switches of the switched capacitor circuit to scale the unscaled input voltage sample and reference voltage and generate an initial residue voltage during a single operation of the initial residue calculation cycle.
摘要翻译： 模数转换器级包括：比较器和逻辑电路，具有不同于上残留电压跳变点和下残余电压跳变点的第一上和下非放大电压跳变点; 和开关电容电路。 比较器和逻辑电路在初始残余计算周期之前配置，以将未缩放输入电压的幅度与第一上限和下限未缩放电压跳变点进行比较，以产生初始输出位，并产生电压缩放和增益控制 信号。 开关电容器电路被配置为对未缩放的输入电压进行采样以接收参考电压，并且接收电压调节和增益控制信号，以选择性地控制开关电容器电路的开关的子集，以缩放未缩放的输入电压样本和参考 并且在初始残留计算周期的单次操作期间产生初始残留电压。
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3.发明授权Optimized reference voltage generation using switched capacitor scaling for data converters 失效使用数据转换器的开关电容器缩放优化参考电压产生公开(公告)号：US06967611B2
公开(公告)日：2005-11-22
申请号：US10804453
申请日：2004-03-19
CPC分类号： H03M1/162
摘要： An algorithmic or cyclic data converter uses an RSD stage having a switched capacitor network for efficiently scaling at least one externally supplied reference voltage. A reference voltage is scaled by using capacitor ratios that also function to provide an output voltage used as a residue output of the RSD A/D converter. The residue is used to generate a bit value corresponding to the magnitude of the residue. Two RSD stages cycle back and forth generating a logic value each half clock cycle until the desired bit resolution is achieved. In one form, the RSD stage scales the externally supplied reference voltage only by factors of less than one. In another form, the RSD stage scales the reference voltage by any scaling factor. A reference voltage scaling circuit separate from the RSD stage is avoided.
摘要翻译： 算法或循环数据转换器使用具有开关电容器网络的RSD级，用于有效地缩放至少一个外部提供的参考电压。 通过使用电容比例来缩放参考电压，该比率也用作提供用作RSD A / D转换器的残留输出的输出电压。 残留物用于产生对应于残基大小的位值。 两个RSD阶段来回循环，每半个时钟周期产生一个逻辑值，直到达到所需的位分辨率。 在一种形式中，RSD级仅通过小于1的因子来缩放外部提供的参考电压。 在另一种形式中，RSD级通过任何缩放因子来缩放参考电压。 避免了与RSD级分离的参考电压缩放电路。
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公开(公告)号：US5606322A
公开(公告)日：1997-02-25
申请号：US327953
申请日：1994-10-24
申请人： Steven P. Allen , Robert J. Durette
发明人： Steven P. Allen , Robert J. Durette
摘要： A method and corresponding apparatus (10) for generating a pseudo-random number. The method has steps of generating a first bit stream from a number generator (16, 35), combining a predetermined number with the first bit stream to provide a second bit stream and feeding the second bit stream into a feedback port (32) of the number generator (16, 35).
摘要翻译： 一种用于产生伪随机数的方法和相应的装置（10）。 该方法具有从数字发生器（16,35）生成第一比特流的步骤，将预定数量与第一比特流组合以提供第二比特流，并将第二比特流馈送到第二比特流的反馈端口（32） 数字发生器（16,35）。
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公开(公告)号：US06909393B2
公开(公告)日：2005-06-21
申请号：US10631450
申请日：2003-07-30
申请人： Ahmad H. Atriss , Steven P. Allen
发明人： Ahmad H. Atriss , Steven P. Allen
IPC分类号： H03M1/06 , H03M1/34 , H03M1/40 , H04B20060101
CPC分类号： H03M1/0695 , H03M1/40
摘要： Methods and apparatus are provided for an analog converter. The apparatus comprises a first redundant signed digit (RSD) stage and a configurable block. The configurable block converts to a sample/hold circuit to sample a single ended analog signal. The sampled signal is then scaled, converted to a differential signal and provided to the first RSD stage. The first RSD stage outputs a bit value corresponding to the magnitude of the digital signal. In a next half clock cycle the first RSD stage calculates a residue that is provided to the configurable block. The configurable block is converted to a second redundant signed digit stage and generates a bit value corresponding to the magnitude of the residue provided by the first RSD stage. The first and second RSD stages cycle back and forth generating logic value each half clock cycle until the desired bit resolution is achieved. The configurable block is then converted back to a sample/hold circuit to start another conversion process.
摘要翻译： 为模拟转换器提供了方法和装置。 该装置包括第一冗余有符号数字（RSD）级和可配置块。 可配置块转换为采样/保持电路以对单端模拟信号进行采样。 然后将取样的信号缩放，转换成差分信号并提供给第一RSD级。 第一RSD级输出与数字信号的幅度对应的位值。 在下一个半时钟周期中，第一RSD级计算提供给可配置块的残差。 可配置块被转换为第二冗余有符号数字级，并且产生对应于由第一RSD级提供的残差幅度的位值。 第一和第二RSD级每个半时钟周期来回循环产生逻辑值，直到达到所需的位分辨率。 然后将可配置块转换回采样/保持电路以开始另一个转换过程。
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公开(公告)号：US4691124A
公开(公告)日：1987-09-01
申请号：US863915
申请日：1986-05-16
申请人： Robert C. Ledzius , Steven P. Allen
发明人： Robert C. Ledzius , Steven P. Allen
摘要： An integrated circuit which contains an on-chip clock that operates the integrated circuit at its true maximum speed is disclosed. The integrated circuit operates asynchronously from a processor bus and contains circuitry for interfacing with the processor bus. A clock generator is constructed using information obtained from identifying a slowest signal path of the integrated circuit. The clock may be stopped and started under processor control to permit communication between the IC and processor bus.
摘要翻译： 公开了一种集成电路，其包含以其真实最大速度操作集成电路的片上时钟。 集成电路从处理器总线异步运行并且包含用于与处理器总线接口的电路。 使用从识别集成电路的最慢信号路径获得的信息来构造时钟发生器。 时钟可以在处理器控制下停止并启动，以允许IC和处理器总线之间的通信。
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7.发明授权Analog to digital conversion architecture and method with input and reference voltage scaling 有权具有输入和参考电压缩放的模数转换结构和方法公开(公告)号：US08823566B2
公开(公告)日：2014-09-02
申请号：US13537308
申请日：2012-06-29
IPC分类号： H03M1/88
摘要： An analog-to-digital converter stage includes: a comparator and logic circuit having first upper and lower unscaled voltage trip points that are different than upper and lower residue voltage trip points; and a switched capacitor circuit. The comparator and logic circuit is configured prior to an initial residue calculation cycle to compare a magnitude of an unscaled input voltage to the first upper and lower unscaled voltage trip points, to generate an initial output bit, and to generate a voltage scaling and gain control signal. The switched capacitor circuit is configured to sample the unscaled input voltage, to receive a reference voltage, and to receive the voltage scaling and gain control signal for selectively controlling a subset of switches of the switched capacitor circuit to scale the unscaled input voltage sample and reference voltage and generate an initial residue voltage during a single operation of the initial residue calculation cycle.
摘要翻译： 模数转换器级包括：比较器和逻辑电路，具有不同于上残留电压跳变点和下残余电压跳变点的第一上和下非放大电压跳变点; 和开关电容电路。 比较器和逻辑电路在初始残余计算周期之前配置，以将未缩放输入电压的幅度与第一上限和下限未缩放电压跳变点进行比较，以产生初始输出位，并产生电压缩放和增益控制 信号。 开关电容器电路被配置为对未缩放的输入电压进行采样以接收参考电压，并且接收电压调节和增益控制信号，以选择性地控制开关电容器电路的开关的子集，以缩放未缩放的输入电压样本和参考 并且在初始残留计算周期的单次操作期间产生初始残留电压。
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公开(公告)号：US08710896B2
公开(公告)日：2014-04-29
申请号：US13484304
申请日：2012-05-31
IPC分类号： H03L5/00 , H03K19/0185
CPC分类号： H03K19/018521
摘要： A sampling switch circuit uses correlated level shifting. The sampling switch circuit includes: a sampling switch having a first terminal, a control terminal, and an output terminal, wherein the first terminal is connected to an input voltage node; a boosting circuit connected to first and second supply voltage nodes and coupled to the control terminal of the sampling switch; and a correlated level shifting buffer circuit. The correlated level shifting buffer circuit includes: an amplifier having first and second inputs and an output, wherein the first input is connected to the input voltage node, and the output and second input are coupled to the boosting circuit; and a level shifting capacitor coupled to the second input and output of the amplifier, to the boosting circuit, and to a level shifting voltage node.
摘要翻译： 采样开关电路使用相关电平转换。 采样开关电路包括：具有第一端子，控制端子和输出端子的采样开关，其中第一端子连接到输入电压节点; 连接到第一和第二电源电压节点并耦合到采样开关的控制端的升压电路; 和相关电平移位缓冲电路。 相关电平移位缓冲电路包括：具有第一和第二输入和输出的放大器，其中第一输入连接到输入电压节点，输出和第二输入耦合到升压电路; 以及耦合到放大器的第二输入和输出，升压电路以及电平转换电压节点的电平移动电容器。
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公开(公告)号：US20130321059A1
公开(公告)日：2013-12-05
申请号：US13484304
申请日：2012-05-31
IPC分类号： H03L5/00
CPC分类号： H03K19/018521
摘要： A sampling switch circuit uses correlated level shifting. The sampling switch circuit includes: a sampling switch having a first terminal, a control terminal, and an output terminal, wherein the first terminal is connected to an input voltage node; a boosting circuit connected to first and second supply voltage nodes and coupled to the control terminal of the sampling switch; and a correlated level shifting buffer circuit. The correlated level shifting buffer circuit includes: an amplifier having first and second inputs and an output, wherein the first input is connected to the input voltage node, and the output and second input are coupled to the boosting circuit; and a level shifting capacitor coupled to the second input and output of the amplifier, to the boosting circuit, and to a level shifting voltage node.
摘要翻译： 采样开关电路使用相关电平转换。 采样开关电路包括：具有第一端子，控制端子和输出端子的采样开关，其中第一端子连接到输入电压节点; 连接到第一和第二电源电压节点并耦合到采样开关的控制端的升压电路; 和相关电平移位缓冲电路。 相关电平移位缓冲电路包括：具有第一和第二输入和输出的放大器，其中第一输入连接到输入电压节点，输出和第二输入耦合到升压电路; 以及耦合到放大器的第二输入和输出，升压电路以及电平转换电压节点的电平移动电容器。
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公开(公告)号：US4794283A
公开(公告)日：1988-12-27
申请号：US54469
申请日：1987-05-26
IPC分类号： H03K3/356 , H03K19/094
CPC分类号： H03K3/356104
摘要： A logic level translator circuit includes capacitive coupling to facilitate rereferencing and differentiating of input logic signals. An input amplifier having complementary devices is responsive to the differentiated signals to provide control signals to a feedback circuit which holds one of the devices in a conductive state and the other in a non-conductive state to provide an output signal having predetermined logic levels. Threshold voltage generating circuits biases each of the devices.
摘要翻译： 逻辑电平转换器电路包括电容耦合以便于重新引用和区分输入逻辑信号。 具有互补器件的输入放大器响应于微分信号，以向控制信号提供控制信号，该反馈电路将器件中的一个保持在导通状态，另一个在非导通状态，以提供具有预定逻辑电平的输出信号。 阈值电压产生电路偏置每个器件。
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