公开(公告)号：US20140337568A1

公开(公告)日：2014-11-13

申请号：US14219281

申请日：2014-03-19

Applicant: SK HYNIX INC.

Inventor： Byoung-Chan Oh ,  Yoon-Jae Shin

IPC: H02M3/04 ,  G06F3/06 ,  G11C5/14

CPC classification number: G06F3/0673 ,  G05F1/465 ,  G05F1/466 ,  G05F1/575 ,  G05F1/70 ,  G05F3/30 ,  G11C5/147 ,  G11C11/1697 ,  G11C13/0038 ,  H02M3/1563

Abstract: Provided is an electronic device including a power supply circuit. The power supply circuit includes: a voltage driving unit configured to pull-up drive an output node and generate an output voltage; and a driving control unit configured to receive the output voltage, disable the voltage driving unit from the time at which a divided voltage obtained by dividing the output voltage at a set ratio becomes higher than a first level, and enable the voltage driving unit from the time at which the divided voltage becomes lower than a second level, which is higher than the first level.

Abstract translation: 提供了一种包括电源电路的电子设备。 电源电路包括：电压驱动单元，被配置为上拉驱动输出节点并产生输出电压; 以及驱动控制单元，被配置为接收所述输出电压，从所述电压驱动单元从通过将所述输出电压除以设定比率而获得的分压值变得高于第一电平的时间来禁用所述电压驱动单元，并且使得所述电压驱动单元从 分压电压变得低于高于第一电平的第二电平的时间。

公开(公告)号：US06847198B2

公开(公告)日：2005-01-25

申请号：US10443043

申请日：2003-05-22

Applicant: Kent M. Kalpakjian ,  John D. Porter

Inventor： Kent M. Kalpakjian ,  John D. Porter

IPC: G05F1/46 ,  G05F1/44 ,  G05F1/40

CPC classification number: G05F1/466

Abstract: A frequency sensing voltage regulator is disclosed. A source follower transistor has a gate connected to a predetermined gate voltage, a drain coupled to an external supply voltage through a switching transistor, and a source connected to a load. The gate of the switching transistor is controlled by a delay circuit through which a pulse derived from the system clock is passed. Through the use of the delay circuit and the switching transistor, the amount of current produced by the source follower transistor is made a function of the cycle rate of the system clock and the current provided by the source follower transistor tracks the frequency-dependent current requirements of the load, resulting in a reduced variance of the supply voltage Vcc over a wide current range.

Abstract translation: 公开了一种频率感测电压调节器。 源极跟随器晶体管具有连接到预定栅极电压的栅极，通过开关晶体管耦合到外部电源电压的漏极和连接到负载的源极。 开关晶体管的栅极由延迟电路控制，通过该延迟电路从系统时钟导出的脉冲通过。 通过使用延迟电路和开关晶体管，由源极跟随器晶体管产生的电流量作为系统时钟的周期速率的函数，并且由源极跟随器晶体管提供的电流跟踪频率相关的电流要求 的负载，导致在宽电流范围内电源电压Vcc的变化减小。

公开(公告)号：US5572159A

公开(公告)日：1996-11-05

申请号：US339328

申请日：1994-11-14

Applicant: Harold L. McFarland

Inventor： Harold L. McFarland

IPC: G05F1/46 ,  G05F3/26 ,  H03K5/00 ,  H03K5/13 ,  H03K17/28

CPC classification number: G05F3/262 ,  G05F1/466 ,  H03K5/131 ,  H03K5/133 ,  H03K2005/00202

Abstract: A voltage-controlled delay element utilizes a current-starved inverter configuration with a feedback path that ensures a rapid discharge of the storage node to ground once the desired delay time has elapsed. The circuit comprises a circuit path for charging the storage node (preferably rapidly), a first pull-down path capable of discharging the storage node at a rate determined by the control voltage, a second pull-down path capable of rapidly discharging the storage node, an output inverter, and a feedback connection between the output terminal of the output inverter and the second pull-down path to rapidly discharge the storage node when the output voltage starts rising. The circuit further comprises a means for programmably adjusting the delay in response to logic signals.

Abstract translation: 电压控制延迟元件利用具有反馈路径的电流饥饿逆变器配置，其确保一旦所需的延迟时间过去，存储节点快速放电到地面。 电路包括用于对存储节点（优选地快速）充电的电路，能够以由控制电压确定的速率对存储节点进行放电的第一下拉路径，能够快速地将存储节点放电的第二下拉路径 输出反相器和输出反相器的输出端子与第二下拉路径之间的反馈连接，以便在输出电压开始上升时快速放电存储节点。 电路还包括用于响应于逻辑信号可编程地调整延迟的装置。

公开(公告)号：US5070257A

公开(公告)日：1991-12-03

申请号：US590098

申请日：1990-09-28

Applicant: William D. Farwell

Inventor： William D. Farwell

IPC: G05F1/46 ,  H03K3/017 ,  H03K17/22 ,  H03K19/003

CPC classification number: H03K3/017 ,  G05F1/466 ,  H03K17/223 ,  H03K19/00315

Abstract: A method and circuitry for controlling the rate of power dissipation of CMOS microcircuits during start-up. In accordance with the invention, either the clock frequency or the duty cycle of clock activity is changed, from zero at the instant of application of the power supply voltage, to the final operating frequency or activity at the end of a warm-up period. As a result, transient temperature differentials between integrated circuit die and the substrates to which they are attached are minimized, increasing the reliability of the CMOS circuitry.

Abstract translation: 用于控制启动时CMOS微电路功耗的方法和电路。 根据本发明，时钟活动的时钟频率或占空比从电源电压施加时的零改变到预热周期结束时的最终工作频率或活动。 因此，集成电路管芯与它们所连接的衬底之间的瞬态温差最小化，从而提高了CMOS电路的可靠性。

公开(公告)号：US4940910A

公开(公告)日：1990-07-10

申请号：US360511

申请日：1989-06-02

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: G05F1/46

CPC classification number: G05F1/466 ,  Y10S323/907

Abstract: A temperature and processing compensated time delay circuit of the type which can be fabricated in a monolithic integrated circuit utilizes a field effect transistor (FET) (12) connected to the terminals of a charged capacitor (14). A bias voltage connected to the gate of the FET (12) varies with temperature in a manner to compensate for the changes in current which flows from the capacitor (14) through the FET (12) due to changes in temperature. The bias voltage also varies from one integrated circuit to another in a manner to compensate for variations in FET threshold voltage caused by variations in the processing of the integrated circuits.

Abstract translation: 可以在单片集成电路中制造的类型的温度和处理补偿时间延迟电路利用连接到充电电容器（14）的端子的场效应晶体管（FET）（12）。 连接到FET（12）的栅极的偏置电压随着温度而变化，以补偿由于温度变化而从电容器（14）流过FET（12）的电流的变化。 偏置电压也可以从一个集成电路到另一个集成电路的变化，以补偿由集成电路的处理变化引起的FET阈值电压的变化。

公开(公告)号：US4862015A

公开(公告)日：1989-08-29

申请号：US163909

申请日：1988-03-03

Applicant: Walter J. Grandfield

Inventor： Walter J. Grandfield

IPC: G05F1/46 ,  H03K3/03 ,  H03L7/099

CPC classification number: H03L7/0805 ,  G05F1/466 ,  H03K3/0315 ,  H03L7/0995

Abstract: A constant propagation delay current reference is provided having an external source providing a reference frequency signal. A phase lock loop is provided which is responsive to the reference frequency signal and to an operating frequency signal to provide a current reference signal at the output of the loop. The current reference signal is provided to a current to frequency converter which generates the operating frequency signal. A current mirror, also coupled to the phase lock loop output provides an output current proportional to the current reference signal which is suitable for providing the injector current for I.sup.2 L devices. The output current tracks the process, voltage and temperature variations of the integrated circuit, allowing the injector currents to be optimized for maintaining constant propagation delay in the circuits being powered.

Abstract translation: 提供了具有提供参考频率信号的外部源的恒定传播延迟电流参考。 提供了一个锁相环，其响应于参考频率信号和工作频率信号，以在环路的输出处提供电流参考信号。 电流参考信号被提供给产生工作频率信号的电流到频率转换器。 还耦合到锁相环输出的电流镜提供与当前参考信号成比例的输出电流，其适于为I2L器件提供注射器电流。 输出电流跟踪集成电路的过程，电压和温度变化，允许喷射器电流被优化，以便在被供电的电路中保持恒定的传播延迟。

公开(公告)号：US5568083A

公开(公告)日：1996-10-22

申请号：US263720

申请日：1994-06-22

Applicant: Akira Uchiyama ,  Ryuji Shibata ,  Yoshinobu Nakagome ,  Masaharu Kubo

Inventor： Akira Uchiyama ,  Ryuji Shibata ,  Yoshinobu Nakagome ,  Masaharu Kubo

IPC: H01L27/04 ,  G05F1/46 ,  G06F1/04 ,  G11C11/407 ,  H01L21/822 ,  H03K19/0175 ,  G05F1/10

CPC classification number: G05F1/466 ,  G05F1/465

Abstract: The semiconductor integrated circuit device incorporates a power supply circuit which forms an operation voltage that matches the operation speed of the internal circuit. Since the operation voltage is set in accordance with the operation speed required of the internal circuit, the internal circuit can be operated with a minimum required voltage even when there are process variations and temperature changes. In other words, a rational power supply is realized.

Abstract translation: 半导体集成电路装置包括形成与内部电路的操作速度相匹配的操作电压的电源电路。 由于操作电压根据内部电路所需的操作速度而设定，即使存在工艺变化和温度变化，内部电路也可以以最小所需电压工作。 换句话说，实现了合理的电源。

公开(公告)号：US5041747A

公开(公告)日：1991-08-20

申请号：US889439

申请日：1986-07-23

Applicant: David P. Chengson ,  H. William Wang

Inventor： David P. Chengson ,  H. William Wang

IPC: G05F1/46 ,  H03K19/003 ,  H03K19/086

CPC classification number: H03K19/086 ,  G05F1/466 ,  H03K19/00323

Abstract: An integrated circuit chip carries a number of electronic circuits, at least one of which includes, in its output stage, a control device that responds to a reference signal to adjust the output current-handling capability of the electronic circuit, thereby regulating the signal propagation delay exhibited by the electronic circuit. The reference circuit is generated by a digital-to-analog circuit that is also formed on the chip. The digital-to-analog circuit is coupled to a number of contact elements disposed on an outer surface of the package containing the integrated circuit chip that can be selectively interconnected to a DC voltage to choose the value of the reference signal.

Abstract translation: 集成电路芯片承载多个电子电路，其中至少一个在其输出级中包括响应参考信号以调整电子电路的输出电流处理能力的控制装置，从而调节信号传播 延迟由电子电路表现出来。 参考电路由也在芯片上形成的数模转换电路产生。 数模转换电路耦合到多个接触元件，该接触元件设置在包含集成电路芯片的封装的外表面上，该集成电路芯片可选择性地互连到直流电压以选择参考信号的值。

公开(公告)号：US4754164A

公开(公告)日：1988-06-28

申请号：US68284

申请日：1984-06-30

Applicant: Laurence P. Flora ,  Michael A. McCullough

Inventor： Laurence P. Flora ,  Michael A. McCullough

IPC: G05F1/46 ,  H03K5/00 ,  H03K5/13 ,  H03K19/003 ,  H05K1/02 ,  H05K3/42 ,  H03K5/159

CPC classification number: H05K1/0248 ,  G05F1/466 ,  H03K19/00323 ,  H03K5/131 ,  H03K2005/00104 ,  H03K2005/00247 ,  H05K2201/09263 ,  H05K2201/09336 ,  H05K3/429

Abstract: A method of providing automatic clock de-skewing for integrated circuit chips carried by a multi-layer circuit board. In a preferred implementation of the method, a clock distribution chip includes on-chip automatic clock de-skewing circuitry requiring an accurate reference delay which is advantageously provided by a strip transmission line formed on one of the conductive planes of the multi-layer circuit board containing the chips.

Abstract translation: 一种为由多层电路板承载的集成电路芯片提供自动时钟去偏移的方法。 在该方法的优选实现中，时钟分配芯片包括片上自动时钟去偏移电路，其需要精确的参考延迟，其有利地由形成在多层电路板的导电平面之一上的带状传输线 包含芯片。

公开(公告)号：US4445083A

公开(公告)日：1984-04-24

申请号：US296382

申请日：1981-08-26

Applicant: John A. DeFalco

Inventor： John A. DeFalco

IPC: G05F1/46 ,  G05F1/56 ,  H01L27/02

CPC classification number: G05F1/466

Abstract: Apparatus adjusts the low supply voltage applied to the bipolar gate array circuits of a semiconductor chip to provide uniform propagation delay in the signals operated on by the array circuits notwithstanding variations in manufacturing tolerances and temperature variations. The apparatus includes a voltage regulator circuit and a first resistor located off the chip connected between its output and adjustment terminals and a second resistor located on the chip connected to the adjustment terminal of the regulator circuit. The voltage regulator circuit in response to changes in the resistance of the second resistor adjusts the low supply voltage at its output terminal so as to provide uniform signal delays through the array circuits.

Abstract translation: 设备调节施加到半导体芯片的双极性栅极阵列电路的低电源电压，以在由阵列电路操作的信号中提供均匀的传播延迟，尽管制造公差和温度变化的变化。 该装置包括电压调节器电路和位于其输出和调节端子之间的芯片上的第一电阻器和位于连接到调节器电路的调整端子的芯片上的第二电阻器。 电压调节器电路响应于第二电阻器的电阻的变化调节其输出端子处的低电源电压，以便通过阵列电路提供均匀的信号延迟。